ARM1176JZF-S Technical Reference Manual: 3.2.57. c15, System Validation Cache Size Mask Register

3.2.57. c15, System Validation Cache Size Mask Register

The purpose of the System Validation Cache Size Mask Register is to change the apparent size of the caches and TCMs as they appear to the processor, for validation by simulation. It does not change the physical size of the caches and TCMs in a manufactured device.

The System Validation Cache Size Mask Register is:

in CP15 c15
a 32 bit read/write register common to the Secure and Non-secure worlds
accessible in User and Privileged modes.

Figure 3.75 shows the arrangement of bits for the System Validation Cache Size Mask Register.

Figure 3.75. System Validation Cache Size Mask Register format

Table 3.146 lists how the bit values correspond with the System Validation Cache Size Mask Register functions.

Table 3.146. System Validation Cache Size Mask Register bit functions

Bits	Field name	Function
[31]	Write enable	Enables the update of the Cache and TCM sizes: 0 = The Cache and TCM sizes are not changed, reset value. 1 = The Cache and TCM sizes take the new values that the DTCM, ITCM, DCache and ICache fields of this register specify. Note This is bit is write access only and Read As Zero.
[30:15]	SBZ	UNP/SBZ.
[14:12]	DTCM	Specifies apparent size of Data TCM and apparent number of Data TCM banks, as it appears to the processor. All other values are reserved: b000 = Not present b011 = 1 bank, 4KB b100 = 2 banks, 4KB each b101 = 2 banks, 8KB each b110 = 2 banks, 16KB each b111 = 2 banks, 32KB each.
[11]	SBZ	UNP/SBZ.
[10:8]	ITCM	Specifies apparent size of Instruction TCM and apparent number of Instruction TCM banks, as it appears to the processor. All other values are reserved: b000 = Not present b011 = 1 bank, 4KB b100 = 2 banks, 4KB each b101 = 2 banks, 8KB each b110 = 2 banks, 16KB each b111 = 2 banks, 32KB each.
[7]	SBZ	UNP/SBZ.
[6:4]	DCache	Specifies apparent size of Data Cache, as it appears to the processor. All other values are reserved: b011 = 4KB b100 = 8KB b101 = 16KB b110 = 32KB b111 = 64KB.
[3]	SBZ	UNP/SBZ.
[2:0]	ICache	Specifies apparent size of Instruction Cache, as it appears to the processor. All other values are reserved: b011 = 4KB b100 = 8KB b101 = 16KB b110 = 32KB b111 = 64KB.

At reset, the values in the System Validation Cache Size Mask Register are the correct values for the implemented caches and TCMs.

Access to the System Validation Cache Size Mask Register in Secure User mode and in the Non-secure world depends on the V bit, see c15, Secure User and Non-secure Access Validation Control Register. Table 3.147 lists the results of attempted access for each mode.

Table 3.147. Results of access to the System Validation Cache Size Mask Register

V bit	Secure Privileged		Non-secure Privileged		User
V bit	Read	Write	Read	Write	Read	Write
0	Data	Data	Undefined exception	Undefined exception	Undefined exception	Undefined exception
1	Data	Data	Data	Data	Data	Data

Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH result in an Undefined exception, see TrustZone write access disable.

To use the System Validation Cache Size Mask Register read or write CP15 with:

Opcode_1 set to 0
CRn set to c15
CRm set to c14
Opcode_2 set to 0.

For example:

                    MRC p15, 0, <Rd>, c15, c14, 0    ; Read System Validation Cache Size Mask Register

                    MCR p15, 0, <Rd>, c15, c14, 0    ; Write System Validation Cache Size Mask Register

You can use the System Validation Cache Size Mask Register, in a validation simulation environment, to perform validation with cache and TCM sizes that appear to be a different size from those that are actually implemented. The validation environment for the processor contains validation RAMs that support cache and TCM size masking using this register. When you write to the System Validation Cache Size Mask Register, the processor behaves as though the caches and TCMs are the sizes that are written to the register. The sizes written to the register are reflected in:

The sizes of the cache and TCM RAMs.
The sizes of the caches in the Cache Type Register, see c0, Cache Type Register, the number of Instruction and Data TCM banks in the TCM Status Register, see c0, TCM Status Register, the sizes of the TCMs in the Instruction TCM Region Register, see c9, Instruction TCM Region Register, and the Data TCM Region Register, see c9, Data TCM Region Register.
The number and use of cache master valid bits, see Cache Master Valid Registers.
The hazard detection logic that prevents the same line being allocated twice into the caches.
The DMA. If the TCMs are both masked as not present, then the DMA also appears not to be present.

Note

You must not modify the System Validation Cache Size Mask Register in a manufactured device. Physical RAMs do not support cache and TCM size masking. Therefore, any attempt to mask cache and TCM sizes using this register causes address aliasing effects and problems with cache master valid bits, that result in incorrect operation and Unpredictable effects.

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