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The purpose of the TLB lockdown access registers is to provide read and write access to the contents of the lockdown region of the TLB. The processor requires these registers to enable it to save state before it enters Dormant mode, see Dormant mode. You might also use this register for debug.
The TLB lockdown access registers are:
in CP15 c15
four 32-bit read/write registers in the Secure world only:
TLB Lockdown Index Register
TLB Lockdown VA Register
TLB Lockdown PA Register
TLB Lockdown Attributes Register.
accessible in privileged modes only.
The four registers have different bit arrangements and functions. Figure 3.76 shows the arrangement of bits in the TLB Lockdown Index Register.
Table 3.148 lists how the bit values correspond with the TLB Lockdown Index Register functions.
Table 3.148. TLB Lockdown Index Register bit functions
| Bits | Field name | Function |
|---|---|---|
| [31:3] | - | UNP/SBZ. |
| [2:0] | Index | Selects the lockdown entry of the eight TLB lockdown entries to read or write when accessing other TLB lockdown access registers. Select lockdown entry 0 to 7. |
Figure 3.77 shows the arrangement of bits in the TLB Lockdown VA Register.
Table 3.149 lists how the bit values correspond with the TLB Lockdown VA Register functions.
Table 3.149. TLB Lockdown VA Register bit functions
| Bits | Field name | Function |
|---|---|---|
| [31:12] | VA | Holds the VA of this page table entry. |
| [11:10] | - | UNP/SBZ. |
| [9] | G | Defines if this page table entry is global, applies to all ASIDs, or application-specific, ASID must match on lookups: 0 = Application-specific entry 1 = Global entry. |
| [8] | - | UNP/SBZ. |
| [7:0] | ASID | Holds the ASID for application-specific page table entries. For global entries, this field Should Be Zero. |
Figure 3.78 shows the arrangement of bits in the TLB Lockdown PA Register.
Table 3.150 lists how the bit values correspond with the TLB Lockdown PA Register functions.
Table 3.150. TLB Lockdown PA Register bit functions
| Bits | Field name | Function |
|---|---|---|
| [31:12] | PA | Holds the PA of this page table entry. |
| [11:10] | - | UNP/SBZ. |
| [9] | NSA | Defines whether memory accesses in the memory region that this page table entry describes are Secure or Non-secure accesses. This matches the Secure or Non-secure state of the memory being accessed. If the NSTID bit is set, the NSA bit is also set regardless of the written value. This ensures that Non-secure page table entries can only access Non-secure memory, but Secure page table entries can access Secure or Non-secure memory: 0 = Memory accesses are Secure 1 = Memory accesses are Non-secure. |
| [8] | NSTID | Defines page table entry as Secure or Non-secure: 0 = Entry is Secure 1 = Entry is Non-secure. |
| [7:6] | Size | Defines the size of the memory region that this page table entry describes: b00 = 16MB supersection b01 = 4KB page b10 = 64KB page b11 = 1M section. |
| [5:4] | - | UNP/SBZ. |
| [3] | APX | Access permissions extension bit. Defines the access permissions for this page table entry. See Table 3.151. |
| [2:1] | AP | Access permissions, or first sub-page access permissions if the page table entry supports sub-pages. |
| [0] | V | Indicates if this page table entry is valid: 0 = Entry is not valid 1 = Entry is valid. |
Table 3.151 lists the encoding for the access permissions for bit fields APX and AP.
Table 3.151. Access permissions APX and AP bit fields encoding
| APX | AP | Supervisor permissions | User permissions | Access type |
|---|---|---|---|---|
| 0 | b00 | No access | No access | All accesses generate a permission fault |
| 0 | b01 | Read/write | No access | Supervisor access only |
| 0 | b10 | Read/write | Read only | Writes in user mode generate permission faults |
| 0 | b11 | Read/write | Read/write | Full access |
| 1 | b00 | No access | No access | Domain fault encoded field |
| 1 | b01 | Read only | No access | Supervisor read only |
| 1 | b10 | Read only | Read only | Supervisor/User read only |
| 1 | b11 | Read only | Read only | Supervisor/User read only |
Figure 3.79 shows the arrangement of bits in the TLB Lockdown Attributes Register.
Table 3.152 lists how the bit values correspond with the TLB Lockdown Attributes Register functions.
Table 3.152. TLB Lockdown Attributes Register bit functions
| Bits | Field name | Function |
|---|---|---|
| [31:30] | AP3 | Sub-page access permissions for the fourth sub-page. If the page table entry does not support sub-pages this field Should Be Zero. |
| [29:28] | AP2 | Sub-page access permissions for the third sub-page. If the page table entry does not support sub-pages this field Should Be Zero. |
| [27:26] | AP1 | Sub-page access permissions for the second sub-page. If the page table entry does not support sub-pages this field Should Be Zero. |
| [25] | SPV | Indicates that this page table entry supports sub-pages. Page table entries that support sub-pages must be marked as Global, see c15, TLB lockdown access registers: 0 = Sub-pages are not valid 1 = Sub-pages are valid. |
| [24:11] | SBZ | UNP/SBZ. |
| [10:7] | Domain | Specifies the Domain number for the page table entry. |
| [6] | XN | Specifies Execute Never attribute: when set, the contents of the memory region that this page table entry describes cannot be executed as code. An attempt to execute an instruction in this region results in a permission fault: 0 = Can execute 1 = Cannot execute. |
| [5:3] | TEX | TEX[2:0] bits. Describes the memory region attributes. See Memory region attributes. |
| [2] | C | C bit. Describes the memory region attributes. See Memory region attributes. |
| [1] | B | B bit. Describes the memory region attributes. See Memory region attributes. |
| [0] | S | Indicates if the memory region that this page table entry describes is shareable: 0 = Region is not shared 1 = Region is shared. |
Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH result in an Undefined exception, see TrustZone write access disable.
Table 3.153 lists the results of attempted access for each mode.
Table 3.153. Results of access to the TLB lockdown access registers
| Secure Privileged | Non-secure Privileged | User | ||
|---|---|---|---|---|
| Read | Write | Read | Write | |
| Data | Data | Undefined exception | Undefined exception | Undefined exception |
To read or write a TLB Lockdown entry, you must use this procedure:
Write TLB Lockdown Index Register to select the required TLB Lockdown entry.
Read or write TLB Lockdown VA Register.
Read or write TLB Lockdown Attributes Register.
Read or write TLB Lockdown PA Register. For writes, this sets the valid bit, enabling the complete new entry to be used.
This procedure must not be interruptible, so your code must disable interrupts before it accesses the TLB lockdown access registers.
Software must avoid the creation of inconsistencies between the main TLB entries and the entries already loaded in the micro-TLBs.
To use the TLB lockdown access registers read or write CP15 with:
Opcode_1 set to 5
CRn set to c15
CRm set to:
c4, TLB Lockdown Index Register
c5, TLB Lockdown VA Register
c6, TLB Lockdown PA Register
c7, TLB Lockdown Attributes Register.
Opcode_2 set to 2.
For example:
MRC p15, 5, <Rd>, c15, c4, 2 ; Read TLB Lockdown Index Register
MCR p15, 5, <Rd>, c15, c4, 2 ; Write TLB Lockdown Index Register
MRC p15, 5, <Rd>, c15, c5, 2 ; Read TLB Lockdown VA Register
MCR p15, 5, <Rd>, c15, c5, 2 ; Write TLB Lockdown VA Register
MRC p15, 5, <Rd>, c15, c6, 2 ; Read TLB Lockdown PA Register
MCR p15, 5, <Rd>, c15, c6, 2 ; Write TLB Lockdown PA Register
MRC p15, 5, <Rd>, c15, c7, 2 ; Read TLB Lockdown Attributes Register
MCR p15, 5, <Rd>, c15, c7, 2 ; Write TLB Lockdown Attributes Register
Example 3.3 is a code sequence that stores all 8 TLB Lockdown entries to memory, and later restores them to the TLB Lockdown region. You might use sequences similar to this for entry into Dormant mode.
Example 3.3. Save and restore all TLB Lockdown entries
ADR r1,TLBLockAddr ; Set r1 to save address
MOV R0,#0 ; Initialize counter
CPSID aif ; Disable interrupts
TLBLockSave MCR p15,5,R0,c15,c4,2 ; Set TLB Lockdown Index
MRC p15,5,R2,c15,c5,2 ; Read TLB Lockdown VA
MRC p15,5,R3,c15,c7,2 ; Read TLB Lockdown Attrs
MRC p15,5,R4,c15,c6,2 ; Read TLB Lockdown PA
STMIA r1!,{R2-R4} ; Save TLB Lockdown entry
ADD R0,R0,#1 ; Increment counter
CMP R0,#8 ; Saved all 8 entries?
BNE TLBLockSave ; Loop until all saved
CPSIE aif ; Re-enable interrupts
; insert other code here
ADR r1,TLBLockAddr ; Set r1 to save address
MOV R0,#0 ; Initialize counter
CPSID aif ; Disable interrupts
TLBLockLoad LDMIA r1!,{R2-R4} ; Load TLB Lockdown entry
MCR p15,5,R0,c15,c4,2 ; Set TLB Lockdown Index
MCR p15,5,R2,c15,c5,2 ; Write TLB Lockdown VA
MCR p15,5,R3,c15,c7,2 ; Write TLB Lockdown Attrs
MCR p15,5,R4,c15,c6,2 ; Write TLB Lockdown PA
ADD R0,R0,#1 ; Increment counter
CMP R0,#8 ; Restored all 8 entries?
BNE TLBLockLoad ; Loop until all restored
CPSIE aif ; Re-enable interrupts
| Copyright © 2004-2009 ARM Limited. All rights reserved. | ARM DDI 0301H |
| Non-Confidential | |
| PDF version | |
| Home > System Control Coprocessor > System control processor registers > c15, TLB lockdown access registers |