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This section contains information on:
The purpose of the Control Register is to provide control and configuration of:
memory alignment, endianness, protection, and fault behavior
MMU and cache enables and cache replacement strategy
interrupts and the behavior of interrupt latency
the location for exception vectors
program flow prediction.
Table 3.39 lists the purposes of the individual bits in the Control Register.
The Control Register is:
in CP15 c1
a 32 bit register, Table 3.39 lists read and write access to individual bits for the Secure and Non-secure worlds
accessible in privileged modes only
partially banked, Table 3.39 lists banked and Secure modify only bits.
Figure 3.26 shows the arrangement of bits in the register.
Table 3.39 lists how the bit values correspond with the Control Register functions.
Table 3.39. Control Register bit functions
Bits | Field name | Access | Function |
|---|---|---|---|
[31:30] | - | - | This field is UNP when read. Write as the existing value. |
| [29] | FA | Banked | This bit controls the Force AP functionality in the MMU that generates Access Bit faults, see Access permissions 0 = Force AP is disabled, reset value. 1 = Force AP is enabled. |
| [28] | TR | Banked | This bit controls the TEX remap functionality in the MMU, see Memory region attributes. 0 = TEX remap disabled. Normal ARMv6 behavior, reset value 1 = TEX remap enabled. TEX[2:1] become page table bits for OS. |
[27:26] | - | - | This field is UNP when read. Write as the existing value. |
| [25] | EE bit | Banked | Determines how the E bit in the CPSR bit is set on an exception. The reset value depends on external signals. 0 = CPSR E bit is set to 0 on an exception, reset value. 1 = CPSR E bit is set to 1 on an exception. |
| [24] | VE bit | Banked | Enables the VIC interface to determine interrupt vectors. See the description of the V bit, bit [13]. 0 = Interrupt vectors are fixed, reset value. 1 = Interrupt vectors are defined by the VIC interface. |
| [23] | XP bit | Banked | Enables the extended page tables to be configured for the hardware page translation mechanism. 0 = Subpage AP bits enabled, reset value. 1 = Subpage AP bits disabled. |
| [22] | U bit | Banked | Enables unaligned data access operations, including support for mixed little-endian and big-endian operation. The A bit has priority over the U bit. The reset value of the U bit depends on external signals. 0 = Unaligned data access support disabled, reset value. The processor treats unaligned loads as rotated aligned data accesses. 1 = Unaligned data access support enabled. The processor permits unaligned loads and stores and support for mixed endian data is enabled. |
| [21] | FI bit | Secure modify only | Configures low latency features for fast interrupts. This bit is overridden by the FIO bit, see c1, Auxiliary Control Register. 0 = All performance features enabled, reset value. 1 = Low interrupt latency configuration enabled. See Low interrupt latency configuration. |
| [20:19] | - | - | UNP/SBZ |
| [18] | IT bit | - | Deprecated. Global enable for instruction TCM. Function redundant in ARMv6. SBO |
| [17] | - | - | UNP/SBZ |
| [16] | DT bit | - | Deprecated. Global enable for data TCM. Function redundant in ARMv6. SBO |
[15] | L4 bit | Secure modify only | Determines if the T bit is set for PC load instructions. For more details see the ARM Architecture Reference Manual. 0 = Loads to PC set the T bit, reset value. 1 = Loads to PC do not set the T bit, ARMv4 behavior. |
[14] | RR bit | Secure modify only | Determines the replacement strategy for the cache. 0 = Normal replacement strategy by random replacement, reset value. 1 = Predictable replacement strategy by round-robin replacement. |
| [13] | V bit | Banked | Determines the location of exception vectors, see c12, Secure or Non-secure Vector Base Address Register and c12, Monitor Vector Base Address Register. The reset value of the V bit depends on an external signal. 0 = Normal exception vectors selected, the Vector Base Address Registers determine the address range, reset value. 1 = High exception vectors
selected, address range = |
| [12] | I bit | Banked | Enables level one instruction cache. 0 = Instruction Cache disabled, reset value. 1 = Instruction Cache enabled. |
| [11] | Z bit | Banked | Enables branch prediction. 0 = Program flow prediction disabled, reset value. 1 = Program flow prediction enabled. |
| [10] | F bit | - | Should Be Zero |
| [9] | R bit | Banked | Deprecated. Enables ROM protection. If you modify the R bit this does not affect the access permissions of entries already in the TLB. See MMU software-accessible registers. 0 = ROM protection disabled, reset value. 1 = ROM protection enabled. |
| [8] | S bit | Banked | Deprecated. Enables MMU protection. If you modify the S bit this does not affect the access permissions of entries already in TLB. 0 = MMU protection disabled, reset value. 1 = MMU protection enabled. |
| [7] | B bit | Secure modify only | Determines operation as little-endian or big-endian word invariant memory system and the names of the low four-byte addresses within a 32-bit word. The reset value of the B bit depends on the BIGENDINIT external signal. 0 = Little-endian memory system, reset value. 1 = Big-endian word-invariant memory system. |
| [6:4] | - | - | This field returns 1 when read. Should Be One. |
| [3] | W bit | - | Not implemented in the processor. Read As One Write Ignore. |
| [2] | C bit | Banked | Enables level one data cache. 0 = Data cache disabled, reset value. 1 = Data cache enabled. |
| [1] | A bit | Banked | Enables strict alignment of data to detect alignment faults in data accesses. The A bit setting takes priority over the U bit. 0 = Strict alignment fault checking disabled, reset value. 1 = Strict alignment fault checking enabled. |
| [0] | M bit | Banked | Enables the MMU. 0 = MMU disabled, reset value. 1 = MMU enabled. |
Attempts to read or write the Control Register from Secure or Non-secure User modes results in an Undefined exception.
Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH result in an Undefined exception, see TrustZone write access disable.
Attempts to write Secure modify only bit in Non-secure privileged modes are ignored.
Attempts to read Secure modify only bits return the Secure bit value. Table 3.40 lists the actions that result from attempted access for each mode.
Table 3.40. Results of access to the Control Register
| Access type | Secure Privileged | Non-secure Privileged | User | |
|---|---|---|---|---|
| Read | Write | |||
| Secure modify only | Secure bit | Secure bit | Ignored | Undefined exception |
| Banked | Secure bit | Non-secure bit | Non-secure bit | Undefined exception |
To use the Control Register it is recommended that you use a read modify write technique. To use the Control Register read or write CP15 with:
Opcode_1 set to 0
CRn set to c1
CRm set to c0
Opcode_2 set to 0.
For example:
MRC p15, 0, <Rd>, c1, c0, 0 ; Read Control Register configuration data
MCR p15, 0, <Rd>, c1, c0, 0 ; Write Control Register configuration data
Normally, to set the V bit and the B, EE, and U bits you configure signals at reset.
The V bit depends on VINITHI at reset:
VINITHI LOW sets V to 0
VINITHI HIGH sets V to 1.
The B, EE, and U bits depend on how you set BIGENDINIT and UBITINIT at reset. Table 3.41 lists the values of the B, EE, and U bits that result for the reset values of these signals. See Reset values of the U, B, and EE bits.
These bits in the Control Register exhibit specific behavior:
The A bit setting takes priority over the U bit. The Data Abort trap is taken if strict alignment is enabled and the data access is not aligned to the width of the accessed data item.
This bit is used in ARM946 and ARM966 processors to enable the Data TCM.
In ARMv6, the TCM blocks have individual enables that apply to each block. As a result, this bit is now redundant and Should Be One. See c9, Data TCM Region Register for a description of the ARM1176JZF-S TCM enables.
This bit is used in ARM946 and ARM966 processors to enable the Instruction TCM.
In ARMv6, the TCM blocks have individual enables that apply to each block. As a result, this bit is now redundant and Should Be One. See c9, Instruction TCM Region Register for a description of the ARM1176JZF-S TCM enables.
Modifying the R bit does not affect the access permissions of entries already in the TLB. See MMU software-accessible registers.
Modifying the S bit does not affect the access permissions of entries already in the TLB. See MMU software-accessible registers.
The ARM1176JZF-S processor does not implement the write buffer enable because all memory writes take place through the Write Buffer.
| Copyright © 2004-2009 ARM Limited. All rights reserved. | ARM DDI 0301H |
| Non-Confidential | |
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