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The purpose of the Instruction TCM Region Register is to describe the physical base address and size of the Instruction TCM region and to provide a mechanism to enable it.
Table 3.87 lists the purposes of the individuals bits of the Instruction TCM Region Register.
The Instruction TCM Region Register is:
in CP15 c9
a 32-bit read/write register common to Secure and Non-secure worlds
accessible in privileged modes only.
If the processor is configured to have 2 Instruction TCMs, each TCM has a separate Instruction TCM Region Register. The TCM Selection Register determines the register in use.
Figure 3.51 shows the bit arrangement for the Instruction TCM Region Register.
Table 3.87 lists how the bit values correspond with the Instruction TCM Region Register functions.
Table 3.87. Instruction TCM Region Register bit functions
| Bits | Field name | Function |
|---|---|---|
[31:12] | Base address | Contains the physical base address of the TCM. The base address must be aligned to the size of the TCM. Any bits in the range [(log2(RAMSize)-1):12] are ignored. The base address is 0 at Reset. |
| [11:7] | - | UNP/SBZ. |
| [6:2] | Size | Indicates the size of the TCM on reads[a]. All other values are reserved: b00000 = 0KB b00011 = 4KB b00100 = 8KB b00101 = 16KB b00110 = 32KB. |
| [1] | - | UNP/SBZ. |
[0] | En | Indicates if the TCM is enabled: 0 = TCM disabled. 1 = TCM enabled. The reset value of this bit depends on the value of the INITRAM static configuration signal. If INITRAM is HIGH then this bit resets to 1. If INITRAM is LOW then this bit resets to 0. For more information see Static configuration signals. |
[a] On writes this field is ignored. For more details see Tightly-coupled memory. | ||
Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH result in an Undefined exception, see TrustZone write access disable.
The value of the En bit at Reset depends on the INITRAM signal:
INITRAM LOW sets En to 0
INITRAM HIGH sets En to 1.
When INITRAM is HIGH this
enables the Instruction TCM directly from reset, with a Base address
of 0x00000. When the processor comes out of reset,
it executes the instructions in the Instruction TCM instead of fetching
instructions from external memory, except when the processor uses
high vectors.
When the NS access bit is 0 for Instruction TCM, see c9, Instruction TCM Non-secure Control Access Register, attempts to access the Instruction TCM Region Register from the Non-secure world cause an Undefined exception.
Table 3.88 lists the results of attempted access for each mode.
Table 3.88. Results of access to the Instruction TCM Region Register
| NS access bit value | Secure Privileged | Non-secure Privileged | User | ||
|---|---|---|---|---|---|
| Read | Write | Read | Write | ||
| 0 | Data | Data | Undefined exception | Undefined exception | Undefined exception |
| 1 | Data | Data | Data | Data | Undefined exception |
To use the Instruction TCM Region Register read or write CP15 with:
Opcode_1 set to 0
CRn set to c9
CRm set to c1
Opcode_2 set to 1.
For example:
MRC p15, 0, <Rd>, c9, c1, 1 ; Read Instruction TCM Region Register
MCR p15, 0, <Rd>, c9, c1, 1 ; Write Instruction TCM Region Register
Attempts to change the Instruction TCM Region Register while a DMA operation is running has Unpredictable effects but there is no impact on security.
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