The B bit in the CP15 c1 Control Register, see Section B2 of the ARM Architecture Reference Manual, determines whether access to stored memory is little-endian or big-endian. The ARM11 processor supports both little-endian and big-endian access formats in memory.

The ARM11 processor stores 32-bit words in memory with the Least Significant Byte (LSB) in the lowest byte of the memory address regardless of the endianness selected. For a store of a single-precision floating-point value, the LSB is located at the target address with the lower two bits of the address cleared. The Most Significant Byte (MSB) is at the target address with the lower two bits set. For best performance, all single-precision data must be aligned in memory to four-byte boundaries, and double-precision data must be aligned to eight-byte boundaries.

Table 19.5 lists how single-precision data is stored in memory and the address to access each byte in both little-endian and big-endian formats. In this example, the target address is 0x40000000.

For double-precision data, the location of the two words that comprise the data are stored in different locations for little-endian and big-endian data access formats. Table 19.6 lists the data storage in memory and the address to access each byte in little-endian and big-endian access modes. In this example, the target address is 0x40000000.

The memory image for the data is identical for both little-endian and big-endian within data words. The ARM11 hardware performs the address transformations to provide both little-endian and big-endian addressing to the programmer.