21.11. Execution timing

Complex instruction dependencies and memory system interactions make it impossible to describe briefly the exact cycle timing of all instructions in all circumstances. The timing that Table 21.16 lists is accurate in most cases. For precise timing, you must use a cycle-accurate model of your ARM11 processor.

In Table 21.16, throughput is defined as the cycle after issue in which another instruction can begin execution. Instruction latency is the number of cycles after which the data is available for another operation. Forwarding reduces the latency by one cycle for operations that depend on floating-point data. Table 21.16 lists the throughput and latency for all VFP11 instructions.

Table 21.16. Throughput and latency cycle counts for VFP11 instructions

InstructionsSingle-precisionDouble-precision
ThroughputLatencyThroughputLatency
FABS, FNEG, FCVT, FCPY1414
FCMP, FCMPE, FCMPZ, FCMPEZ1414
FSITO, FUITO, FTOSI, FTOUI, FTOUIZ, FTOSIZ1818
FADD, FSUB1818
FMUL, FNMUL1829
FMAC, FNMAC, FMSC, FNMSC1829
FDIV, FSQRT15192933
FLD[a]

1

414
FSTa

1a

System- dependent1System- dependent
FLDMaX[b]Xb + 3XbXb + 3
FSTMaXbSystem- dependentXbSystem- dependent
FMSTAT12--
FMSR/FMSRR[c]14--
FMDHR/FMDHC/FMDRRc--14
FMRS/FMRRSc12--
FMRDH/FMRDL/FMRRDc--12
FMXR[d]14--
FMRXd12--

[a] The cycle count for a load instruction is based on load data that is cached and available to the ARM11 processor from the cache. The cycle count for a store instruction is based on store data that is written to the cache and/or write buffer immediately. When the data is not cached or the write buffer is unavailable, the number of cycles also depends on the memory subsystem.

[b] The number of cycles represented by X is (N/2) if N is even or (N/2 + 1) if N is odd.

[c] FMDRR and FMRRD transfer one double-precision data per transfer. FMSRR and FMRRS transfer two single-precision data per transfer.

[d] FMXR and FMRX are serializing instructions. The latency depends on the register transferred and the current activity in the VFP11 coprocessor when the instruction is issued.


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