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The Secure control bus ETMIASECCTL indicates when the processor is in Secure state and when the data trace is prohibited.
Table 15.3 lists the signals in the Secure control bus ETMIASECCTL.
Table 15.3. ETMIASECCTL[1:0]
| Bits | Reference name | Description | Qualified by |
|---|---|---|---|
| [1] | IASProhibited | Trace prohibited for this instruction | IAValid |
| [0] | IASNonSecure | Instruction executed in Non-secure state | IAValid |
| Copyright © 2004-2009 ARM Limited. All rights reserved. | ARM DDI 0301H |
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| Home > Trace Interface Port > About the ETM interface > Secure control bus |