ARM1176JZF-S Technical Reference Manual: 20.4. VFP11 system registers

20.4. VFP11 system registers

The VFPv2 architecture describes the following three system registers that must be present in a VFP system:

Floating-Point System ID Register, FPSID
Floating-Point Status and Control Register, FPSCR
Floating-Point Exception Register, FPEXC.

The VFP11 coprocessor provides sufficient information for processing all exceptional conditions encountered by the hardware. In an exceptional situation, the hardware provides:

the exceptional instruction
the instruction that might have been issued to the VFP11 coprocessor before detection of the exception
exception status information:
- type of exception
- number of remaining short vector iterations after an exceptional iteration.

To support exceptional conditions, the VFP11 coprocessor provides two additional registers:

Floating-Point Instruction Register, FPINST
Floating-Point Instruction Register 2, FPINST2.

Also, the FPEXC register contains additional bits to support exceptional conditions.

These registers are designed to be used with the support code software available from ARM Limited. As a result, this document does not fully specify exception handling in all cases.

The coprocessor also provides two feature registers:

Media and VFP Feature Register 0, MVFR0
Media and VFP Feature Register 1, MVFR1.

Table 20.3 lists the VFP11 system registers.

Table 20.3. VFP11 system registers

Register	Access mode	Access type	Reset state	See
Floating-Point System ID Register, FPSID	Any	Read-only	`0x410120B3`	Floating-Point System ID Register, FPSID
Floating-Point Status and Control Register, FPSCR	Any	Read/write	`0x00000000`	Floating-Point Status and Control Register, FPSCR
Floating-Point Exception Register, FPEXC	Privileged	Read/write	`0x00000000`	Floating-point exception register, FPEXC
Floating-Point Instruction Register, FPINST	Privileged	Read/write	`0xEE000A00`	Instruction registers, FPINST and FPINST2
Floating-Point Instruction Register 2, FPINST2	Privileged	Read/write	UNP	Instruction registers, FPINST and FPINST2
Media and VFP Feature Register 0, MVFR0	Any	Read-only	`0x11111111`	Media and VFP Feature Register 0
Media and VFP Feature Register 1, MVFR1	Any	Read-only	`0x00000000`	Media and VFP Feature Register 1

Use the FMRX instruction to transfer the contents of VFP11 registers to ARM11 registers and the FMXR instruction to transfer the contents of ARM11 registers to VFP11 registers.

Table 20.4 lists the ARM11 processor modes for accessing the VFP11 system registers.

Table 20.4. Accessing VFP11 system registers

	FMXR/FMRX <reg> field	ARM11 processor mode
Register	FMXR/FMRX <reg> field	VFP11 coprocessor enabled	VFP11 coprocessor disabled
FPSID	b0000	Any mode	Privileged mode
FPSCR	b0001	Any mode	None^[a]
FPEXC	b1000	Privileged mode	Privileged mode
FPINST	b1001	Privileged mode	Privileged mode
FPINST2	b1010	Privileged mode	Privileged mode
MVFR0	b0111	Any mode	Privileged mode
MVFR1	b0110	Any mode	Privileged mode
^[a]An instruction that tries to access FPSCR while the VFP11 coprocessor is disabled takes the Undefined Instruction trap.

Table 20.4 shows that a privileged ARM11 mode is sometimes required to access a VFP11 system register. When a privileged mode is required, an instruction that tries to access a register in a nonprivileged mode takes the Undefined Instruction trap.

The following sections describe the VFP11 system registers:

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