The TCM is designed to provide low-latency memory that can be used by the processor without the unpredictability that is a feature of caches.

You can use such memory to hold critical routines, such as interrupt handling routines or real-time tasks where the indeterminacy of a cache is highly undesirable. In addition you can use it to hold scratch pad data, data types whose locality properties are not well suited to caching, and critical data structures such as interrupt stacks.

You can separately configure the size of the Instruction TCM (ITCM) and the size of the Data TCM (DTCM) to be 0KB, 4KB. 8KB, 16KB, 32KB or 64KB. For each side, ITCM and DTCM:

Table 7.1 lists all possible TCM configurations:

When the number of TCM on one side is 2, to make the implementation easier, the TCM for this side are implemented as one single RAM. This RAM then has a size in the 0-64 KB range. The lower part of the RAM corresponds to the TCM called TCM0 and the upper part corresponds to TCM1.

You can also configure each individual TCM to contain Secure or Non-secure data. You make this configuration in CP15 register c9, accessible in Secure state only. See c9, Data TCM Non-secure Control Access Register and c9, Instruction TCM Non-secure Control Access Register for more information. After reset, all TCMs are configured as Secure.

The TCM Status Register in CP15 c0 describes what TCM options and TCM sizes can be implemented, see c0, TCM Status Register.

Each Data TCM is implemented in parallel with the Data Cache and each Instruction TCM is implemented in parallel with the Instruction Cache. Each TCM has a single movable base address, specified in CP15 register c9, see c9, Data TCM Region Register and c9, Instruction TCM Region Register.

The size of each TCM can differ from the size of a cache way, but forms a single contiguous area of memory. Figure 7.1 shows the entire level one memory system. To access each of the TCM region and TCM Access Control registers, the TCM Selection registers are set to the TCM of interest, see c9, TCM Selection Register.

The base address of each TCM can be placed anywhere in the physical address map, and does not have to be backed by memory implemented externally. The Instruction and Data TCMs have separate base addresses.

You can disable each TCM to avoid an access being made to it. This gives a reduction in the power consumption. You can disable each TCM independently from the enabling of the associated cache, as determined by CP15 register c9. The disabling of a TCM invalidates the base address, so there is no unexpected hit behavior for the TCM.

The timing of a TCM access is the same as for a cache access. The ARM1176JZF-S processor does not support wait states on the TCM interfaces.

Table 7.2 lists the access types for TCM configured as Non-secure.

Table 7.3 lists the access types for TCM configured as Secure.