ARM1176JZF-S Technical Reference ManualRevision: r0p7
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22.4.3. Exception processing for CDP short vector instructions

For short vector instructions, any iteration might be exceptional. If an exceptional condition is detected for a vector iteration, the vector iterations issued before the exceptional iteration are permitted to complete and retire.

When a short vector iteration is found to be potentially exceptional, the following operations occur:

  1. The EX flag, FPEXC[31], is set.

  2. The source and destination register addresses are modified in the instruction word to point to the source and destination registers of the potentially exceptional iteration.

  3. The FPINST register is loaded with the operation instruction word.

  4. The VECITR field, FPEXC[10:8], is written with the number of iterations remaining after the potentially exceptional iteration.

  5. The exceptional condition flags are set in the FPEXC.

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