1.10. ARM1176JZF-S instruction set summary

This section provides:

Table 1.6 lists a key to the ARM and Thumb instruction set tables.

The ARM1176JZF-S processor implements the ARM architecture v6 with ARM Jazelle technology. For a description of the ARM and Thumb instruction sets, see the ARM Architecture Reference Manual. Contact ARM Limited for complete descriptions of all instruction sets.

Table 1.6. Key to instruction set tables

SymbolDescription
{!}Update base register after operation if ! present.
{^}For all STMs and LDMs that do not load the PC, stores or restores the User mode banked registers instead of the current mode registers if ^ present, and sets the S bit. For LDMs that load the PC, indicates that the CPSR is loaded from the SPSR.
BByte operation.
HHalfword operation.
TForces execution to be handled as having User mode privilege. Cannot be used with pre-indexed addresses.
x

Selects HIGH or LOW 16 bits of register Rm. T selects the HIGH 16 bits,

T = top, and B selects the LOW 16 bits, B = bottom.

y

Selects HIGH or LOW 16 bits of register Rs. T selects the HIGH 16 bits,

T = top, and B selects the LOW 16 bits, B = bottom.

{cond}Updates condition flags if cond present. See Table 1.15.
{field}See Table 1.14.
{S}Sets condition codes, optional.
<a_mode2>See Table 1.8.
<a_mode2P>See Table 1.9.
<a_mode3>See Table 1.10.
<a_mode4>See Table 1.11.
<a_mode5>See Table 1.12.
<cp_num>One of the coprocessors p0 to p15.
<effect>

Specifies the effect required on the interrupt disable bits, A, I, and F in the CPSR:

IE = Interrupt enable

ID = Interrupt disable.

<iflags> specifies the bits affected if <effect> is specified.

<endian_specifier>

BE = Set E bit in instruction, set CPSR E bit.

LE = Reset E bit in instruction, clear CPSR E bit.

<HighReg>Specifies a register in the range R8 to R15.
<iflags>

A sequence of one or more of the following:

a = Set A bit.

i = Set I bit.

f = Set F bit.

If <effect> is specified, the sequence determines the interrupt flags that are affected.

<immed_8*4>A 10-bit constant, formed by left-shifting an 8-bit value by two bits.
<immed_8>An 8-bit constant.
<immed_8r>A 32-bit constant, formed by right-rotating an 8-bit value by an even number of bits.
<label>The target address to branch to.
<LowReg>Specifies a register in the range R0 to R7.
<mode>The new mode number for a mode change. See Mode bits.
<op1>, <op2>Specify, in a coprocessor-specific manner, the coprocessor operation to perform.
<operand2>See Table 1.13.
<option>Specifies additional instruction options to the coprocessor. An integer in the range 0 to 255 surrounded by { and }.
<reglist>A comma-separated list of registers, enclosed in braces {and}.
<rotation>One of ROR #8, ROR #16, or ROR #24.
<Rm>Specifies the register, the value of which is the instruction operand.
<Rn>Specifies the address of the base register.
<shift>

Specifies the optional shift. If present, it must be one of:

  • LSL #N. N must be in the range 0 to 31.

  • ASR #N. N must be in the range 1 to 32.


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