| Copyright © 2004-2009 ARM Limited. All rights reserved. | ARM DDI 0301H |
| Non-Confidential | |
 PDF version | |
| Home > Programmer’s Model > Exceptions > Exception entry and exit summary |
| |||
| Home > Programmer’s Model > Exceptions > Exception entry and exit summary | |||
Table 2.8 summarizes the PC value preserved in the relevant R14 on exception entry, and the recommended instruction for exiting the exception handler. Full details of Jazelle state exceptions are provided in the Jazelle V1 Architecture Reference Manual.
Table 2.8. Exception entry and exit
Exception or entry | Return instruction | Previous state | Notes | ||
|---|---|---|---|---|---|
ARM R14_x | Thumb R14_x | Jazelle R14_x | |||
SVC | MOVS PC, R14_svc | PC + 4 | PC+2 | - | Where the PC is the address of the SVC, SMC, or undefined instruction. Not used in Jazelle state. |
SMC | MOVS PC, R14_mon | PC + 4 | - | - | |
UNDEF | MOVS PC, R14_und | PC + 4 | PC+2 | - | |
PABT | SUBS PC, R14_abt, #4 | PC + 4 | PC+4 | PC+4 | Where the PC is the address of instruction that had the Prefetch Abort. |
FIQ | SUBS PC, R14_fiq, #4 | PC + 4 | PC+4 | PC+4 | Where the PC is the address of the instruction that was not executed because the FIQ or IRQ took priority. |
IRQ | SUBS PC, R14_irq, #4 | PC + 4 | PC+4 | PC+4 | |
DABT | SUBS PC, R14_abt, #8 | PC + 8 | PC+8 | PC+8 | Where the PC is the address of the Load or Store instruction that generated the Data Abort. |
RESET | NA | - | - | - | The value saved in R14_svc on reset is Unpredictable. |
BKPT | SUBS PC, R14_abt, #4 | PC + 4 | PC+4 | PC+4 | Software breakpoint. |
| Copyright © 2004-2009 ARM Limited. All rights reserved. | ARM DDI 0301H |
| Non-Confidential | |
| PDF version | |
| Home > Programmer’s Model > Exceptions > Exception entry and exit summary |