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SCR[3:1] determine the mode that the processor enters on an FIQ, IRQ, or external abort exception, see System control and configuration.
When handling an ARM exception the processor:
Preserves the address of the next instruction in the appropriate LR. When the exception entry is from:
The processor writes the value of the PC into the LR, offset by a value, current PC + 4 or PC + 8 depending on the exception, that causes the program to resume from the correct place on return.
The processor writes the value of the PC into the LR, offset by a value, current PC + 2, PC + 4 or PC + 8 depending on the exception, that causes the program to resume from the correct place on return.
The exception handler does not have to determine the state
when entering an exception. For example, in the case of a SVC, MOVS
PC, R14_svc always returns to the next instruction regardless
of whether the SVC was executed in ARM or Thumb state.
Copies the CPSR into the appropriate SPSR.
Forces the CPSR mode bits to a value that depends on the exception.
Forces the PC to fetch the next instruction from the relevant exception vector.
The processor can also set the interrupt and imprecise abort disable flags to prevent otherwise unmanageable nesting of exceptions.
Exceptions are always entered, handled, and exited in ARM state. When the processor is in Thumb state or Jazelle state and an exception occurs, the switch to ARM state takes place automatically when the exception vector address is loaded into the PC.
| Copyright © 2004-2009 ARM Limited. All rights reserved. | ARM DDI 0301H |
| Non-Confidential | |
| PDF version | |
| Home > Programmer’s Model > Exceptions > Entering an ARM exception |