| Copyright © 2004-2009 ARM Limited. All rights reserved. | ARM DDI 0301H |
| Non-Confidential | |
 PDF version | |
| Home > System Control Coprocessor > System control processor registers > Register allocation |
| |||
| Home > System Control Coprocessor > System control processor registers > Register allocation | |||
Table 3.2 lists the allocation and reset values of the registers of the system control coprocessor where:
CRn is the register number within CP15
Op1 is the Opcode_1 value for the register
CRm is the operational register
Op2 is the Opcode_2 value for the register.
Type applies to the Secure, S, or the Non-secure, NS, world and is:
B, registers banked in Secure and Non-secure worlds. If the registers are not banked then they are common to both worlds or only accessible in one world.
NA, no access
RO, read-only access
RO, read-only access in privileged modes only
R/W, read/write access
R/W, read/write access in privileged modes only
WO, write-only access
WO, write-only access in privileged modes only
X, access depends on another register or external signal.
Table 3.2. Summary of CP15 registers and operations
| CRn | Op1 | CRm | Op2 | Register or operation | S type | NS type | Reset value | Page |
|---|---|---|---|---|---|---|---|---|
| c0 | 0 | c0 | 0 | Main ID | RO | RO | 0x41xFB76x [a] | c0, Main ID Register |
| 1 | Cache Type | RO | RO | 0x10152152 [b] | c0, Cache Type Register | |||
| 2 | TCM Status | RO | RO | 0x00020002 [c] | c0, TCM Status Register | |||
| 3 | TLB Type | RO | RO | 0x00000800 | c0, TLB Type Register | |||
| c1 | 0 | Processor Feature 0 | RO | RO | 0x00000111 | c0, Processor Feature Register 0 | ||
| 1 | Processor Feature 1 | RO | RO | 0x00000011 | c0, Processor Feature Register 1 | |||
| 2 | Debug Feature 0 | RO | RO | 0x00000033 | c0, Debug Feature Register 0 | |||
| 3 | Auxiliary Feature 0 | RO | RO | 0x00000000 | c0, Auxiliary Feature Register 0 | |||
| 4 | Memory Model Feature 0 | RO | RO | 0x01130003 | c0, Memory Model Feature Register 0 | |||
| 5 | Memory Model Feature 1 | RO | RO | 0x10030302 | c0, Memory Model Feature Register 1 | |||
| 6 | Memory Model Feature 2 | RO | RO | 0x01222100 | c0, Memory Model Feature Register 2 | |||
| 7 | Memory Model Feature 3 | RO | RO | 0x00000000 | c0, Memory Model Feature Register 3 | |||
| c2 | 0 | Instruction Set Feature Attribute 0 | RO | RO | 0x00140011 | c0, Instruction Set Attributes Register 0 | ||
| 1 | Instruction Set Feature Attribute 1 | RO | RO | 0x12002111 | c0, Instruction Set Attributes Register 1 | |||
| 2 | Instruction Set Feature Attribute 2 | RO | RO | 0x11231121 | c0, Instruction Set Attributes Register 2 | |||
| 3 | Instruction Set Feature Attribute 3 | RO | RO | 0x01102131 | c0, Instruction Set Attributes Register 3 | |||
| 4 | Instruction Set Feature Attribute 4 | RO | RO | 0x00001141 | c0, Instruction Set Attributes Register 4 | |||
| 5 | Instruction Set Feature Attribute 5 | RO | RO | 0x00000000 | c0, Instruction Set Attributes Register 5 | |||
| 6-7 | Reserved | - | - | - | - | |||
| c3-c7 | - | Reserved | - | - | - | - | ||
| c1 | 0 | c0 | 0 | Control | R/W, B[d], X | R/W | 0x00050078[e] | c1, Control Register |
| 1 | Auxiliary Control | R/W | RO | 0x00000007 | c1, Auxiliary Control Register | |||
| 2 | Coprocessor Access Control | R/W | R/W | 0x00000000 | c1, Coprocessor Access Control Register | |||
| c1 | 0 | Secure Configuration | R/W | NA | 0x00000000 | c1, Secure Configuration Register | ||
| 1 | Secure Debug Enable | R/W | NA | 0x00000000 | c1, Secure Debug Enable Register | |||
| 2 | Non-Secure Access Control | R/W | RO | 0x00000000 | c1, Non-Secure Access Control Register | |||
| c2 | 0 | c0 | 0 | Translation Table Base 0 | R/W, B, X | R/W | 0x00000000 | c2, Translation Table Base Register 0 |
| 1 | Translation Table Base 1 | R/W, B | R/W | 0x00000000 | c2, Translation Table Base Register 1 | |||
| 2 | Translation Table Base Control | R/W, B, X | R/W | 0x00000000 | c2, Translation Table Base Control Register | |||
| c3 | 0 | c0 | 0 | Domain Access Control | R/W, B, X | R/W | 0x00000000 | c3, Domain Access Control Register |
| c4 | Not used | |||||||
| c5 | 0 | c0 | 0 | Data Fault Status | R/W, B | R/W | 0x00000000 | c5, Data Fault Status Register |
| 1 | Instruction Fault Status | R/W, B | R/W | 0x00000000 | c5, Instruction Fault Status Register | |||
| c6 | 0 | c0 | 0 | Fault Address | R/W, B | R/W | 0x00000000 | c6, Fault Address Register |
| 1 | Watchpoint Fault Address | R/W | NA | 0x00000000 | c6, Watchpoint Fault Address Register | |||
| 2 | Instruction Fault Address | R/W, B | R/W | 0x00000000 | c6, Instruction Fault Address Register | |||
| c7 | 0 | c0 | 4 | Wait For Interrupt | WO | WO | - | Wait For Interrupt operation |
| c4 | 0 | PA | R/W, B | R/W | 0x00000000 | PA Register | ||
| c5 | 0 | Invalidate Entire Instruction Cache | WO | WO, X | - | Invalidate, Clean, and Prefetch operations | ||
| 1 | Invalidate Instruction Cache Line by MVA | WO | WO | - | Invalidate, Clean, and Prefetch operations | |||
| 2 | Invalidate Instruction Cache Line by Index | WO | WO | - | Invalidate, Clean, and Prefetch operations | |||
| 4 | Flush Prefetch Buffer | WO | WO | - | Flush operations | |||
| 6 | Flush Entire Branch Target Cache | WO | WO | - | Flush operations | |||
| 7 | Flush Branch Target Cache Entry by MVA | WO | WO | - | Flush operations | |||
| c6 | 0 | Invalidate Entire Data Cache | WO | NA | - | Invalidate, Clean, and Prefetch operations | ||
| 1 | Invalidate Data Cache Line by MVA | WO | WO | - | Invalidate, Clean, and Prefetch operations | |||
| 2 | Invalidate Data Cache Line by Index | WO | WO | - | Invalidate, Clean, and Prefetch operations | |||
| c7 | 0 | Invalidate Both Caches | WO | NA | - | Invalidate, Clean, and Prefetch operations | ||
| c8 | 0-3 | VA to PA translation in the current world | WO | WO | - | VA to PA translation in the current world | ||
| 4-7 | VA to PA translation in the other world | WO | NA | - | VA to PA translation in the other world | |||
| c7 | 0 | c10 | 0 | Clean Entire Data Cache | WO, X | WO, X | - | Invalidate, Clean, and Prefetch operations |
| 1 | Clean Data Cache Line by MVA | WO | WO | - | Invalidate, Clean, and Prefetch operations | |||
| 2 | Clean Data Cache Line by Index | WO | WO | - | Invalidate, Clean, and Prefetch operations | |||
| 4 | Data Synchronization Barrier | WO | WO | - | Data Synchronization Barrier operation | |||
| 5 | Data Memory Barrier | WO | WO | - | Data Memory Barrier operation | |||
| 6 | Cache Dirty Status | RO, B | RO | 0x00000000 | Cache Dirty Status Register | |||
| c13 | 1 | Prefetch Instruction Cache Line | WO | WO | - | Invalidate, Clean, and Prefetch operations | ||
| c14 | 0 | Clean and Invalidate Entire Data Cache | WO, X | WO, X | - | Invalidate, Clean, and Prefetch operations | ||
| 1 | Clean and Invalidate Data Cache Line by MVA | WO | WO | - | Invalidate, Clean, and Prefetch operations | |||
| 2 | Clean and Invalidate Data Cache Line by Index | WO | WO | - | Invalidate, Clean, and Prefetch operations | |||
| c8 | 0 | c5 | 0 | Invalidate Instruction TLB unlocked entries | WO, B | WO | - | c8, TLB Operations Register |
| 1 | Invalidate Instruction TLB entry by MVA | WO, B | WO | - | c8, TLB Operations Register | |||
| 2 | Invalidate Instruction TLB entry on ASID match | WO, B | WO | - | c8, TLB Operations Register | |||
| c8 | 0 | c6 | 0 | Invalidate Data TLB unlocked entries | WO, B | WO | - | c8, TLB Operations Register |
| 1 | Invalidate Data TLB entry by MVA | WO, B | WO | - | c8, TLB Operations Register | |||
| 2 | Invalidate Data TLB entry on ASID match | WO, B | WO | - | c8, TLB Operations Register | |||
| c7 | 0 | Invalidate unified TLB unlocked entries | WO, B | WO | - | c8, TLB Operations Register | ||
| 1 | Invalidate unified TLB entry by MVA | WO, B | WO | - | c8, TLB Operations Register | |||
| 2 | Invalidate unified TLB entry on ASID match | WO, B | WO | - | c8, TLB Operations Register | |||
| c9 | 0 | c0 | 0 | Data Cache Lockdown | R/W | R/W, X | 0xFFFFFFF0 | c9, Data and instruction cache lockdown registers |
| 1 | Instruction Cache Lockdown | R/W | R/W, X | 0xFFFFFFF0 | c9, Data and instruction cache lockdown registers | |||
| c1 | 0 | Data TCM Region | R/W, X | R/W, X | 0x00000014[f] | c9, Data TCM Region Register | ||
| 1 | Instruction TCM Region | R/W, X | R/W, X | 0x00000014[g] | c9, Instruction TCM Region Register | |||
| 2 | Data TCM Non-secure Control Access | R/W, X | NA | 0x00000000 | c9, Data TCM Non-secure Control Access Register | |||
| 3 | Instruction TCM Non-secure Control Access | R/W, X | NA | 0x00000000 | c9, Instruction TCM Non-secure Control Access Register | |||
| c2 | 0 | TCM Selection | R/W, B | R/W | 0x00000000 | c9, TCM Selection Register | ||
| c8 | 0 | Cache Behavior Override | R/W[h] | R/W | 0x00000000 | c9, Cache Behavior Override Register | ||
| c10 | 0 | c0 | 0 | TLB Lockdown | R/W, X | R/W, X | 0x00000000 | c10, TLB Lockdown Register |
| c2 | 0 | Primary Region Memory Remap Register | R/W, B, X | R/W | 0x00098AA4 | c10, Memory region remap registers | ||
| 1 | Normal Memory Region Remap Register | R/W, B, X | R/W | 0x44E048E0 | c10, Memory region remap registers | |||
| c11 | 0 | c0 | 0-3 | DMA identification and status | RO | RO, X | 0x0000000B[i] | c11, DMA identification and status registers |
| c1 | 0 | DMA User Accessibility | R/W | R/W, X | 0x00000000 | c11, DMA User Accessibility Register | ||
| c2 | 0 | DMA Channel Number | R/W, X | R/W, X | 0x00000000 | c11, DMA Channel Number Register | ||
| c3 | 0-2 | DMA enable | WO, X | WO, X | - | c11, DMA enable registers | ||
| c4 | 0 | DMA Control | R/W, X | R/W, X | 0x08000000 | c11, DMA Control Register | ||
| c5 | 0 | DMA Internal Start Address | R/W, X | R/W, X | - | c11, DMA Internal Start Address Register | ||
| c6 | 0 | DMA External Start Address | R/W, X | R/W, X | - | c11, DMA External Start Address Register | ||
| c7 | 0 | DMA Internal End Address | R/W, X | R/W, X | - | c11, DMA Internal End Address Register | ||
| c8 | 0 | DMA Channel Status | RO, X | RO, X | 0x00000000 | c11, DMA Channel Status Register | ||
| c15 | 0 | DMA Context ID | R/W | R/W, X | - | c11, DMA Context ID Register | ||
| c12 | 0 | c0 | 0 | Secure or Non-secure Vector Base Address | R/W, B, X | R/W | 0x00000000 | c12, Secure or Non-secure Vector Base Address Register |
| 1 | Monitor Vector Base Address | R/W, X | NA | 0x00000000 | c12, Monitor Vector Base Address Register | |||
| c1 | 0 | Interrupt Status | RO | RO | 0x00000000[j] | c12, Interrupt Status Register | ||
| c13 | 0 | c0 | 0 | FCSE PID | R/W, B, X | R/W | 0x00000000 | c13, FCSE PID Register |
| 1 | Context ID | R/W, B | R/W | 0x00000000 | c13, Context ID Register | |||
| 2 | User Read/Write Thread and Process ID | R/W, B | R/W | 0x00000000 | c13, Thread and process ID registers | |||
| 3 | User Read-only Thread and Process ID | R/W, RO, B[k] | R/W, RO | 0x00000000 | c13, Thread and process ID registers | |||
| 4 | Privileged Only Thread and Process ID | R/W, B | R/W | 0x00000000 | c13, Thread and process ID registers | |||
| c14 | Not used | |||||||
| c15 | 0 | c2 | 4 | Peripheral Port Memory Remap | R/W, B, X | R/W | 0x00000000 | c15, Peripheral Port Memory Remap Register |
| c9 | 0 | Secure User and Non-secure Access Validation Control | R/W, X | NA | 0x00000000 | c15, Secure User and Non-secure Access Validation Control Register | ||
| c12 | 0 | Performance Monitor Control | R/W, X | R/W, X | 0x00000000 | c15, Performance Monitor Control Register | ||
| 1 | Cycle Counter | R/W, X | R/W, X | 0x00000000 | c15, Cycle Counter Register | |||
| 2 | Count 0 | R/W, X | R/W, X | 0x00000000 | c15, Count Register 0 | |||
| 3 | Count 1 | R/W, X | R/W, X | 0x00000000 | c15, Count Register 1 | |||
| 4-7 | System Validation Counter | R/W, X | R/W, X | 0x00000000 | c15, System Validation Counter Register | |||
| c13 | 1-7 | System Validation Operations | R/W, X | R/W, X | 0x00000000 | c15, System Validation Operations Register | ||
| c14 | 0 | System Validation Cache Size Mask | R/W, X | R/W, X | 0x00006655[l] | c15, System Validation Cache Size Mask Register | ||
| c15 | 1 | c13 | 0-7 | System Validation Operations | R/W, X | R/W, X | 0x00000000 | c15, System Validation Operations Register |
| c15 | 2 | c13 | 1-7 | System Validation Operations | R/W, X | R/W, X | 0x00000000 | c15, System Validation Operations Register |
| c15 | 3 | c8 | 0-7 | Instruction Cache Master Valid | R/W, X | NA | 0x00000000 | c15, Instruction Cache Master Valid Register |
| c12 | 0-7 | Data Cache Master Valid | R/W, X | NA | 0x00000000 | c15, Data Cache Master Valid Register | ||
| c13 | 0-7 | System Validation Operations | R/W, X | R/W, X | 0x00000000 | c15, System Validation Operations Register | ||
| c15 | 4 | c13 | 0-7 | System Validation Operations | R/W, X | R/W, X | 0x00000000 | c15, System Validation Operations Register |
| c15 | 5 | c4 | 2 | TLB Lockdown Index | R/W, X | NA | 0x00000000 | c15, TLB lockdown access registers |
| c5 | 2 | TLB Lockdown VA | R/W, X | NA | - | c15, TLB lockdown access registers | ||
| c6 | 2 | TLB Lockdown PA | R/W, X | NA | - | c15, TLB lockdown access registers | ||
| c7 | 2 | TLB Lockdown Attributes | R/W, X | NA | - | c15, TLB lockdown access registers | ||
| c13 | 0-7 | System Validation Operations | R/W, X | R/W, X | 0x00000000 | c15, System Validation Operations Register | ||
| c15 | 6 | c13 | 0-7 | System Validation Operations | R/W, X | R/W, X | 0x00000000 | c15, System Validation Operations Register |
| c15 | 7 | c13 | 0-7 | System Validation Operations | R/W, X | R/W, X | 0x00000000 | c15, System Validation Operations Register |
[a] See c0, Main ID Register for the values of bits [23:20] and bits [3:0]. [b] Reset value depends on the cache size implemented. The value here is for 16KB instruction and data caches. [c] Reset value depends on the number of TCM banks implemented. The value here is for 2 data TCM and 2 instruction TCM banks. [d] Some bits in this register are banked and some Secure modify only. [e] Reset value depends on external signals. [f] Reset value depends on the TCM sizes implemented. The value here is for 16KB TCM banks. [g] Reset value depends on the TCM sizes implemented, and on the value of the INITRAM static configuration signal. The value here is for 16KB TCM banks, with INITRAM tied LOW. [h] Some bits in this register are common and some Secure modify only. [i] Reset value depends on the number of DMA channels implemented and the presence of TCMs. [j] Reset value depends on external signals. [k] This register is read/write in Privileged modes and read-only on User mode. [l] Reset value depends on the cache and TCM sizes implemented. The value here is for 2 banks of 16KB instruction and data TCMs and 16KB instruction and data caches. | ||||||||
Table 3.3 lists the operations available with MCRR operations:
MCRR{cond} P15,<Opcode_1>,<End Address>,<Start Address>,<CRm>
Table 3.3. Summary of CP15 MCRR operations
| Op1 | CRm | Register or operation | S type | NS type | Reset value | Page |
|---|---|---|---|---|---|---|
| 0 | c5 | Invalidate instruction cache range | WO | WO | - | c7, Cache operations |
| c6 | Invalidate data cache range | WO | WO | - | c7, Cache operations | |
| c12 | Clean data cache range | WO | WO | - | c7, Cache operations | |
| c14 | Clean and invalidate data cache range | WO | WO | - | c7, Cache operations |
| Copyright © 2004-2009 ARM Limited. All rights reserved. | ARM DDI 0301H |
| Non-Confidential | |
| PDF version | |
| Home > System Control Coprocessor > System control processor registers > Register allocation |