8.5.28. Cacheable Write-Through or Noncacheable
STM5
Table 8.54 shows
the values of AWADDRRW, AWBURSTRW, AWSIZERW,
and AWLENRW for STM5s to words
0 to 3 over the Data Read/Write Interface.
An STM5 to words 4 to 7 is split into two operations as shown
in Table 8.55.
Table 8.54. Cacheable Write-Through or Noncacheable STM5 to word 0, 1,
2, or 3
| Address[4:0] | AWADDRRW | AWBURSTRW | AWSIZERW | AWLENRW | First WSTRBRW |
|---|
0x00, word 0 | 0x00 | Incr | 32-bit | 5 data transfers | b0000 1111 |
0x04, word 1 | 0x04 | Incr | 32-bit | 5 data transfers | b1111 0000 |
0x08, word 2 | 0x08 | Incr | 32-bit | 5 data transfers | b0000 1111 |
0x0C, word 3 | 0x0C | Incr | 32-bit | 5 data transfers | b1111 0000 |
Table 8.55. Cacheable Write-Through or Noncacheable STM5 to word 4, 5,
6, or 7
| Address[4:0] | Operations |
|---|
0x10, word 4 | STM4 to 0x10 + STR to 0x00 |
0x14, word 5 | STM3 to 0x14 + STM2 to 0x00 |
0x18, word 6 | STM2 to 0x18 + STM3 to 0x00 |
0x1C, word 7 | STR to 0x1C + STM4 to 0x00 |
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