1.2. ARM L210 MBIST Controller interface

Figure 1.1 shows the ARM L210 MBIST Controller interface to the Automated Test Equipment (ATE) and to the MBIST interface of the ARM L210.

Figure 1.1. ARM L210 MBIST Controller wiring diagram

Figure 1.2 shows the traditional method of accessing a cache RAM for MBIST.

Figure 1.2. Traditional method of interfacing MBIST

Because this method significantly reduces the maximum operating frequency, it is not suitable for high-performance designs. Instead, the ARM L210 MBIST Controller uses an additional input to the existing functional multiplexers without reducing maximum operating frequency.

Figure 1.3 shows the five pipeline stages used to access the cache RAM arrays.

Figure 1.3. MBIST interface of the ARM L210

The ARM L210 MBIST Controller accesses memory through the MBIST interface of the ARM L210. Table 1.1 lists the ARM L210 MBIST interface signals.

Table 1.1. Signals of the ARM L210 MBIST interface

NameI/ODescription
nRESETInputGlobal active LOW reset signal.
CLKInputActive HIGH clock signal. This clock drives the ARM L210 logic.
MBISTDOUT[63:0]Output

Data out bus from all cache RAM blocks.

MBISTDCTL[12:0]InputDelayed versions of the MBISTCE[10:0] signal and the doubleword select signal, MBISTADDR[1:0]. Selects the correct read data after it passes through the MBIST pipeline stages.MBISTDCTL[12:0] = delayed {MBISTCE[10:0]MBISTADDR[1:0]}.
MTESTONInput

Select signal for cache RAM array. This signal is the select input to the multiplexers that access the cache RAM arrays for test. When asserted, MTESTON takes priority over all other select inputs to the multiplexers.

MBISTCE[10:0]Input

One-hot chip enable signals to select cache RAM arrays for test.

MBISTWEInput

Global write enable signal for all RAM arrays.

MBISTADDR[17:0]Input

Address signal for cache RAM array. MBISTADDR[1:0] is the doubleword select value. See Y addr and xaddr fields, MBIR[23:20] and MBIR[27:24] for a description of the doubleword select. Not all RAM arrays use the full address width.

MBISTDIN[63:0]Input

Data bus to the cache RAM arrays. Not all RAM arrays use the full data width.

Note

The interface of the ARM L210 MBIST Controller communicates with both the ATE and the MBIST interface of the ARM L210. See Appendix A Signal Descriptions for descriptions of the interface signals of the ARM L210 MBIST Controller. See the ARM L210 Technical Reference Manual for more details on the MBIST interface of the ARM L210.

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