3.2.5. Y addr and xaddr fields, MBIR[23:20] and MBIR[27:24]

The number of address bits you must specify for a RAM can be determined from the MBIR fields:

This enables you to specify your address range in two dimensions, which represents the topology of the physical implementation of the RAM more accurately. These two dimensions are controlled by two separate address counters, the x-address counter and the y-address counter. One counter can be incremented or decremented only when the other counter has expired. The chosen test algorithm determines which counter moves faster.

Use this procedure to determine how many bits to assign to the x-address and y-address counters:

  1. Determine the column width of the RAM array. The y-address must have at least that many bits for the column select. If it is a data RAM, then add two bits to that number for the doubleword select.

  2. Determine how many address bits the RAM requires (see ARM L210 RAMs). Subtract the current y-address bit number from that number. If the result is eight or fewer bits, then they are all assigned to the x-address for the row select. Otherwise, eight bits are used for the x-address and any unassigned bits are added to the bits already assigned to the y-address and used for the block select.

Figure 3.2 is an example topology for the data RAM in a 256K level-2 cache.

Figure 3.2. Example data RAM topology

The cache RAM in Figure 3.2 has a column width of 16, so it uses four bits for the column address. These four bits map to the least significant bits of the y-address counter. Because this is a data RAM, it requires two additional doubleword select bits. The doubleword select bits choose between the four 64-bit groups of RAM data before sending the data to the 64-bit MBISTDOUT[63:0] bus. These two bits always map to the y-address counter bits between the column address and the block address.

Because this cache RAM has 256 rows per column, it uses eight bits for the row address, which uses up all eight bits of the x-address counter. This RAM also contains two blocks of 16 columns each, so it uses one bit for the block address, which maps to the most significant bit of the y-address counter. To correctly test this RAM, the y addr field must have a value of seven (MBIR[23:20] = b0111), and the X addr field must have a value of eight (MBIR[27:24] = b1000). Values higher or lower than these produce incorrect results.

Note

If the columns have fewer than 256 rows, you must still assign address bits to the row address until all eight bits are used before assigning any to the block address. If the cache RAM has more than 256 rows per column, then the additional bits must be assigned to the block address. This does not have any detrimental effects on the test coverage of the RAM.

Figure 3.3 shows how the ARM L210 MBIST Controller builds the address output. The doubleword select bits are the least significant two bits of the address. These two bits are ignored unless the data RAM is selected. The exclusive OR of the two least significant bits of the y-address counter is the least significant bit of the column address for physical addressing of the columns. This is followed by the row address from the x-address counter and, if required, the block address.

Figure 3.3. MBIST address scrambling

Y addr

The y addr field specifies the number of y-address counter bits to use during test. Table 3.4 lists the y addr settings.

Table 3.4. Y addr field encoding

Y addr MBIR[23:0]Number of counter bits
<b0010Unsupported
b00102
b00113
b01004
b01015
b01106
b01117
b10008
b10019
b101010
>b1010Reserved

X addr

The x addr field specifies the number of x-address counter bits to use during test. Table 3.5 lists the x addr settings.

Table 3.5. X addr field encoding

X addr MBIR[27:24]Number of counter bits
<b0010Unsupported
b00102
b00113
b01004
b01015
b01106
b01117
b10008
>b1000Reserved

ARM L210 RAMs

Table 3.6 shows the required sums of the x addr and y addr fields for complete testing of each RAM type.

Table 3.6. Required sums of x addr and y addr fields

Cache sizeData RAMData parity RAMTag or dirty RAMs
128K14129
256K151310
512K161411
1M171512
2M181613
Copyright © 2003, 2004 ARM Limited. All rights reserved.ARM DDI 0302C
Non-Confidential