3.1. About the MBIST Instruction Register

Figure 3.1 shows the bit fields of the MBIR.

Figure 3.1. Memory BIST Instruction Register

The MBIR fields set up the behavior of the MBIST engine:

Cache size

Specifies a cache size of 128KB, 256KB, 512KB, 1MB, or 2MB.

Column width

Specifies 4, 8, 16, or 32 columns per block of RAM.

Enables

Specifies the RAM under test.

Data seed

Specifies the four-bit data background.

Y addr

Specifies the number of bits in the y-address counter.

X addr

Specifies the number of bits in the x-address counter.

Read latency

Specifies the number of cycles to allow for a RAM read.

Write latency

Specifies the number of cycles to allow for a RAM write.

Control

Specifies MBIST mode of operation and sticky or nonsticky fail flag.

Pattern

Specifies the test algorithm.

Field descriptions describes the MBIR fields in more detail.

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