A.1. Signal descriptions

Table A.1 lists the ARM L210 MBIST Controller interface signals.

Table A.1. Signals of the ARM L210 MBIST Controller interface

PinI/ODescription
CLKInputActive HIGH clock signal. This clock drives the ARM L210 MBIST Controller logic.
MBISTDOUT[63:0]Input

Data out bus from all RAM arrays.

MBISTDCTL[12:0]Output

Delayed versions of the MBISTCE[10:0] signal and the doubleword select signal, MBISTADDR[1:0]. Selects the correct read data after it passes through the MBIST pipeline stages.

MBISTDCTL[12:0] = delayed {MBISTCE[10:0]MBISTADDR[1:0]}.

MBISTRESETNInputActive LOW reset signal for the ARM L210 MBIST Controller logic. This signal must be asserted for at least one full CLK cycle before programming the controller for the first test.
MTESTONInputRAM array select signal. This signal is the select input to the multiplexers that access the RAM arrays for test. MTESTON also enables the registers in the L210 MBIST Controller to clock in new data.
MBISTDSHIFTInputShift out. Asserting this signal enables serial unload of the data log.
MBISTRUNInputTest run. Asserting this signal begins the programmed test algorithm.
MBISTSHIFTInputShift in. Asserting this signal enables serial load of the MBIST Instruction Register.
MBISTDATAINOutputSerial data input for loading the MBIST Instruction Register.
MBISTRESULT[2:0]Output

ARM L210 MBIST Controller output. This signal provides test status and serial data log output:

MBISTRESULT[2] = test complete flag, asserted at the end of the test

MBISTRESULT[1] = fail flag, asserted when failure is detected

MBISTRESULT[0] = address expire flag or data log output. During testing, this signal goes HIGH each time both the x-address and y-address counters expire, which indicates progression to the next stage of the selected test pattern. When shifting out the data log, this signal is the serial data output.

MBISTCE[10:0]Output

One-hot chip enable signals to select RAM blocks for test.

MBISTWEOutput

Global write enable signal for all RAM arrays.

MBISTADDR[17:0]Output

RAM array address signal. MBISTADDR[1:0] is the doubleword select value. See Y addr and xaddr fields, MBIR[23:20] and MBIR[27:24] for a description of the doubleword select. Not all RAM arrays use the full address width.

MBISTDIN[63:0]Output

Data bus to the RAM arrays. Not all RAM arrays use the full data width.

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