1.1.4. Intelligent Energy Controller

The Intelligent Energy Controller (IEC) is designed for reuse in a wide variety of AMBA based designs and has a standard APB slave interface for programming the registers. This provides an Applications Programming Interface (API) for the IEM software. The IEC connects through defined interfaces to SoC-specific components such as the DVC.

The IEC uses prediction performance level requests from the IEM software. The performance setting is communicated to the IEC so that the System-on-Chip specific and product platform scaling hardware can be controlled to bring the system to that performance point. Battery life is extended by lowering the operating frequency and voltage of SoC components, such as the processor, and consequently reducing energy consumption.

The IEC provides an abstracted view of the SoC-specific performance scaling hardware. It is responsible for translating the performance prediction made by the IEM software (0-100% of maximum performance) into an appropriate performance point at which the system runs and then controlling the scaling hardware to achieve operation at that target point. This is achieved through passing a target performance request to the DCG and DVC.

The IEC also measures the work done in the system to ensure that the software deadlines are not going to be missed. Additionally, the IEC supports a maximum performance hardware request feature.

The IEC is designed to map to an implementation-defined set of index levels. You must configure the IEC to define the DCG frequencies and DVC voltage levels that can be selected. These frequencies and voltages depend on the capabilities of the dynamic or adaptive power supply technology to support multiple operating performance points.

The IEC interfaces to the DCG and DVC blocks through a thermometer encoded interface protocol, that indicates to the IEC the current performance level. This protocol is specified to support interfacing across asynchronous clock domains between high-speed PLL and clock-generator and low-speed voltage scaling hardware. The IEC provides an encoded performance index to SoC specific DCG and DVC blocks.

An additional feature of the encoding is that it supports operation between one or more IEC-enabled processing subsystems and one or more DVCs. That is, it is multiprocessor enabled.

The IEC also includes a Design for Test (DFT) interface. This enables easier control over the scaling hardware during production testing of the SoC device.

The IEC configuration and thermometer encoded interfaces are described in more detail later in the document, see:


The IEC is an AMBA compliant, SoC peripheral that is developed, tested, and licensed by ARM Limited. The IEC features are as follows:

  • AMBA APB compliant.

  • Defined interfaces between the IEC and the other on-chip peripherals that are necessary for a complete energy management solution:

    • DCG

    • DVC.

  • An abstract interface to the underlying system-specific clock multiplexing and dynamic voltage or power control. This is through mapping to an implementation-defined set of index levels:

    • that correspond with the DCG frequencies that can be selected, and

    • that enable the voltage steps for the corresponding dynamic or adaptive power supply technology and consequently supports multiple operating performance points.

  • An encoded interface protocol that provides a performance index to SoC specific DCG and DVC blocks.

  • Signaling codes to support operation between one or more IEC-enabled processing subsystems and one or more DVCs. It is therefore multiprocessor enabled.

  • Dynamic Voltage Scaling (DVS) emulation support enables a run fast then idle mode of operation.

  • An API interface for efficient control and monitoring:

    • implementation-independent fractional performance setting interface to support performance prediction algorithms without hard-coded frequencies.

    • implementation-independent interrogation of performance-level quantization mapping levels to enable performance prediction software to adapt to the processor clock frequencies provided.

    • SoC-specific configuration interrogation, consisting of processor and IEC clock frequencies in kHz, and performance level mapping provided by the SoC specific DCG.

  • Support for maximum performance signaling for real time subsystems that enables:

    • the maximum performance level to be requested regardless of the current programmed target performance level.

    • you to decide the events that activate this mode.

  • Monitoring for IEM-specific algorithms, through a multi-channel interface designed to support automatic accumulation of system metrics.

  • Support for synchronization handshaking with synchronous and asynchronous bridges to control entry and exit from maximum performance mode.

  • Test registers for use in block and system level integration testing.

  • System level integration testing using externally applied integration vectors.

  • Debug mode for testing clock generation with maximum voltage.

  • ID support registers for porting software driver compliance.

  • DFT interface to control the target index outputs during SoC DFT.

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