A.1.11. DFT interface

DFT interfaceTable A.11 shows the DFT interface signals.

Table A.11. DFT interface signals

SignalTypeSource or destinationDescription
IECDFTCLAMPInputTest controller

This signal can be used during scan test of the SoC, to ensure that all target index outputs from the IEC are static.

  • When IECDFTCLAMP is 1:

    • IECTGTDVCIDX[7:0] and IECTGTDCGIDX[7:0] outputs are set to 100%, that is, set to all 1's.

  • When IECDFTCLAMP is 0:

    • IECTGTDVCIDX[7:0] and IECTGTDCGIDX[7:0] outputs are set to normal behavior.

IECDFTPERFCNTLInputTest controller

Performance control override for DFT.

  • When IECDFTPERFCNTL is 1:

    • IECTGTDVCIDX[7:0] and IECTGTDCGIDX[7:0] outputs are set to the values as presented on the IECDFTTGTDVCIDX[7:0] and IECDFTTGTDCGIDX[7:0] inputs respectively.

  • When IECDFTPERFCNTL is 0:

    • IECTGTDVCIDX[7:0] and IECTGTDCGIDX[7:0] outputs are set to normal behavior and the state of the IECDFTTGTDVCIDX[7:0] and IECDFTTGTDCGIDX[7:0] inputs is irrelevant.

IECDFTTGTDCGIDX[7:0]InputTest controllerTarget index for DCG when IECDFTPERFCNTL is asserted. Uses the same encoding as the IECTGTDCGIDX[7:0] outputs.
IECDFTTGTDVCIDX[7:0]InputTest controllerTarget index for DVC when IECDFTPERFCNTL is asserted. Uses the same encoding as the IECTGTDVCIDX[7:0] outputs.
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