A.1.9. DVS emulation

Table A.9 shows the DVS emulation interface signals.

Table A.9. DVS emulation signals

SignalTypeSource or destinationDescription
IECDVSEMCLKENInputClock generatorThe enable for advancing the PWM frame time slots when in DVS emulation mode. This signal must be pulsed at a frequency of 1MHz.
IECPWRREQOutputDVCRequest for maximum/minimum voltage when in DVS emulation mode.
Copyright © 2003, 2008 ARM Limited. All rights reserved.ARM DDI 0304C
Non-Confidential