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Table A.9 shows the DVS emulation interface signals.
Table A.9. DVS emulation signals
| Signal | Type | Source or destination | Description |
|---|---|---|---|
| IECDVSEMCLKEN | Input | Clock generator | The enable for advancing the PWM frame time slots when in DVS emulation mode. This signal must be pulsed at a frequency of 1MHz. |
| IECPWRREQ | Output | DVC | Request for maximum/minimum voltage when in DVS emulation mode. |
| Copyright © 2003, 2008 ARM Limited. All rights reserved. | ARM DDI 0304C |
| Non-Confidential | |
| PDF version | |
| Home > Signal Descriptions > IEC signals > DVS emulation |