Intelligent Energy Controller Technical Reference Manual 3.3.26. Peripheral Identification Registers

3.3.26. Peripheral Identification Registers

The Peripheral Identification Registers are eight, 8-bit read-only registers. They span two address locations:

IECPeriphID0-3 Registers span address locations 0xFE0-0xFEC
IECPeriphID4-7 Registers span address locations 0xFD0-0xFDC

Each of these blocks of registers 0-3 and 4-7 can conceptually be treated as one 32-bit read-only register. The IECPeriphID0-3 Registers provide the peripheral options listed in Table 3.28.

Table 3.28. Peripheral Identification Register options, IECPeriphID0-3

Bits	Description
Configuration 1[31:24]	The configuration option of the peripheral.
Revision number[23:20]	The revision number of the peripheral. The revision number starts from 0.
Designer[19:12]	The designer identification. ARM Limited is `0x41`, ASCII A.
Part number[11:0]	The peripheral, using the three digit product code. The IEC code is `0x750`.

Note

When you design a systems memory map then you must remember that the register has a 4KB-memory footprint. All memory accesses to the peripheral identification registers must be 32-bit, using the LDR and STR instructions.

Figure 3.15 shows the bit assignments for the IECPeriphID0-3 Registers.

Figure 3.15. Peripheral Identification Register bit assignments, IECPeriphID0-3

The IECPeriphID4-7 Registers provide the peripheral options listed in Table 3.29.

Table 3.29. Peripheral Identification Register options, IECPeriphID4-7

Bits		Description
Configuration 5[31:24]		Reserved, read undefined
Configuration 4[23:16]		Reserved, read undefined
Configuration 3[15:8]		The configuration option of the peripheral
Configuration 2[7:0]		The configuration option of the peripheral

Figure 3.16 shows the bit assignments for the IECPeriphID4-7 Registers.

Figure 3.16. Peripheral Identification Register bit assignments, IECPeriphID4-7

The eight, 8-bit peripheral identification registers are described in the following subsections:

Peripheral Identification Register 0

The IECPeriphID0 Register is read-only. It is hard coded and the fields in the register determine the reset value. Table 3.30 lists the register bit assignments.

Table 3.30. IECPeriphID0 Register bit assignments

Bits	Name	Description
[31:8]	-	Reserved, read undefined
[7:0]	Partnumber0	These bits read back as `0x50`

Peripheral Identification Register 1

The IECPeriphID1 Register is read-only. It is hard coded and the fields in the register determine the reset value. Table 3.31 lists the register bit assignments.

Table 3.31. IECPeriphID1 Register bit assignments

Bits	Name	Description
[31:8]	-	Reserved, read undefined
[7:4]	Designer0	These bits read back as `0x1`
[3:0]	Partnumber1	These bits read back as `0x7`

Peripheral Identification Register 2

The IECPeriphID2 Register is read-only. It is hard coded and the fields in the register determine the reset value. Table 3.32 lists the register bit assignments.

Table 3.32. IECPeripID2 Register bit assignments

Bits	Name	Description
[31:8]	-	Reserved, read undefined
[7:4]	Revision	These bits read back as `0x1`
[3:0]	Designer1	These bits read back as `0x4`

Peripheral Identification Register 3

The IECPeriphID3 Register is read-only. It is hard coded and the fields in the register determine the reset value. Table 3.33 lists the register bit assignments.

Table 3.33. IECPeriphID3 Register bit assignments

Bits	Name	Description
[31:8]	-	Reserved, read undefined.
[7:0]	Configuration1	Number of DPC levels. These bits read back as `0x08.`

The configuration field is used to indicate the Number of DPC levels. This is the maximum number of levels supported in the hardware.

Peripheral Identification Register 4

The IECPeriphID4 Register is read-only. It is hard coded and the fields in the register determine the reset value. Table 3.34 lists the register bit assignments.

Table 3.34. IECPeriphID4 Register bit assignments

Bit	Name	Description
[31:8]	-	Reserved, read undefined.
[7:3]	Reserved
[2:0]	Configuration 2	Number of DPM channels. These bits read back as `0x3`.

The configuration field is used to indicate the number of DPM channels. This is the number of Dynamic Performance channels supported in the hardware. The control attributes for channels 1 to DPMCHANNELS (inclusive) are supported, all other channels are unimplemented and reserved.

Peripheral Identification Register 5

The IECPeriphID5 Register is read-only. It is hard coded and the fields in the register determine the reset value. Table 3.35 lists the register bit assignments

Table 3.35. IECPeriphID5 Register bit assignments

Bits	Name	Description
[31:8]	-	Reserved, read undefined.
[7:0]	Configuration 3	Number of DVS slots in a frame. These bits read back as `0x08`.

The configuration field is used to indicate the number of slots in a DVS emulation frame. This determines the number of supported performance levels available in the DVS emulation mode.

Peripheral Identification Register 6

The IECPeriphID6 Register is read-only. It is hard coded and the fields in the register determine the reset value. Table 3.36 lists the register bit assignments

Table 3.36. IECPeriphID6 Register bit assignments

Bits	Name	Description
[31:8]	-	Reserved, read undefined
[7:0]	Configuration 4	These bits are all reserved

Peripheral Identification Register 7

The IECPeriphID7 Register is read-only. It is hard coded and the fields in the register determine the reset value. Table 3.37 lists the register bit assignments

Table 3.37. IECPeriphID7 Register bit assignments

Bits	Name	Description
[31:8]	-	Reserved, read undefined
[7:0]	Configuration 5	These bits are all reserved

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