This glossary describes some of the terms used in this manual. Where terms can have several meanings, the meaning presented here is intended.

Advanced Microcontroller Bus Architecture (AMBA)

AMBA is the ARM open standard for multi-master on-chip buses, capable of running with multiple masters and slaves. It is an on-chip bus specification that details a strategy for the interconnection and management of functional blocks that make up a System-on-Chip (SoC). It aids in the development of embedded processors with one or more CPUs or signal processors and multiple peripherals. AMBA complements a reusable design methodology by defining a common backbone for SoC modules. APB conforms to this standard.

Advanced Peripheral Bus (APB)

The AMBA Advanced Peripheral Bus is a simpler bus protocol than AHB. It is designed for use with ancillary or general-purpose peripherals such as timers, interrupt controllers, UARTs, and I/O ports. Connection to the main system bus is through a system-to-peripheral bus bridge that helps to reduce system power consumption.


See Advanced Microcontroller Bus Architecture.


See Advanced Peripheral Bus.

Advanced Power Controller (APC)

The NSC on-chip IP block that interfaces between the IEC, the HPM, the DCG and external power supplies conforming to the PowerWise™ Interface.


The organization of hardware and/or software that characterizes a processor and its attached components, and enables devices with similar characteristics to be grouped together when describing their behavior, for example, Harvard architecture, instruction set architecture, ARMv6 architecture.

Central Processing Unit (CPU)

The part of a processor that contains the ALU, the registers, and the instruction decode logic and control circuitry. Also commonly known as the processor core.


See Central Processing Unit.

Dynamic Clock Generator (DCG)

A system-specific clock generator that has an IEC-compliant performance setting and monitoring interface. It also interfaces to the Advanced Power Controller (APC) and the Hardware Performance Monitor (HPM).

Dynamic Performance Controller (DPC)

A functional part of the IEC. The DPC translates the target performance level into index values for the DCG and DVC interfaces. It also performs reverse mapping when the IEM software reads the current performance level

Dynamic Performance Monitor (DPM)

A functional part of the IEC. The DPM provides hardware support for the IEM software to monitor the work done for various tasks. Three channels are available. Each channel is in the form of a 64-bit accumulator that counts the fractional performance every PCLK clock cycle when IECDPMCLKEN is HIGH.

Dynamic Voltage Controller (DVC)

A system specific block that controls an off-chip power supply unit and interfaces to the IEC and DCG blocks

Dynamic Voltage Scaling (DVS)

Support for controlling the multi-level power supply to a subsystem to reduce voltage when less than 100% of the performance is required by the subsystem. This is achieved using dynamic software control.

Energy Management Unit (EMU)

The NSC implementation of a PSU that works closely with the APC to provide a closed loop voltage scaling solution.

Intelligent Energy Controller (IEC)

The component that provides a standard API interface for the IEM software to set performance levels regardless of any system specific blocks such as the DVC and the DCG. It also provides monitoring functions through the DPM.

Intelligent energy management

A process to enable prolonged battery life of a device by dynamically controlling the power level.

Intelligent Energy Manager (IEM)

An energy manager solution consisting of both software and hardware components that function together to prolong battery life in a device.

Implementation- defined

A feature that is not architecturally defined, and can vary between implementations. The feature is defined and documented for each individual implementation.


A contraction of microprocessor. A processor includes the CPU or core, plus additional components such as memory, and interfaces. These are combined as a single macrocell, that can be fabricated on an integrated circuit.


A temporary storage location used to hold binary data until it is ready to be used.


A field in a control register or instruction format is reserved if the field is to be defined by the implementation, or produces Unpredictable results if the contents of the field are not zero. These fields are reserved for use in future extensions of the architecture or are implementation-specific. All reserved bits not used by the implementation must be written as zero and are read as zero.

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