The IEC provides hardware support for the IEM software to monitor the work done. Three channels are available. Each channel is in the form of a 64-bit accumulator that counts the fractional performance by incrementing the channel value with the current channel rate (0-32). The rate that each of the channels accumulates is described in the following sections.
On reset all channels are frozen and held at their reset values.
Because the channels are 64-bit wide and the APB interface of the IEC is 32-bit, the software has to read each channel in a defined sequence. The low bits of the channel must be read first followed by the high bits of the channel. The IEC ensures that the high bits of the channel are stored when the low bits of the corresponding channel are read.
The clocking for each of the channels is identical, and uses PCLK. However, each channel only increments on a rising edge of PCLK when the channel clock enable input, IECDPMCLKEN is HIGH. The design of the channels assumes that IECDPMCLKEN is synchronously derived from PCLK. This enables you to operate the channels at a lower effective frequency than PCLK. That is, IECDPMCLKEN is pulsed HIGH at the required frequency synchronous to PCLK. This relationship is shown in Figure 2.7.
Note
These notes are for additional information only and not connected to Figure 2.7.
IECDPMCLKEN can also be tied HIGH resulting in the channels being clocked at the PCLK frequency, and this might lead to a high power solution. In this case, the IECCFGFREQDPM must be tied to indicate the PCLK frequency.
The minimum recommended frequency to pulse IECDPMCLKEN is 1MHz.
The frequency of PCLK must always be faster than the frequency that IECDPMCLKEN is pulsed.
The rate that Channel 1 accumulates is dependent on the fractional performance that the processor is currently running at. The rate is taken from the current DCG clock status IECCRNTDCGIDX. That is, the rate for channel 1 changes whenever a new fractional performance level is programmed and the DCG changes to a different clock frequency. That is, on every update cycle, the value in IECCRNTDCGIDX[7:0] is added to the Channel 1.
The rates that channels 2 and 3 accumulate are software programmable. You can program the IECDPM2RATE and IECDPM3RATE Registers to set the rate that channels 2 and 3, respectively, accumulate. The IEM software can use this for a number of different functions depending on the monitoring algorithms that it is executing.
PDF version