2.2.9. DVS emulation with PWM

The IEC has a mode of operation to enable support for systems that do not implement voltage scaling but still want to be able to do performance scaling. This enables reuse of the DVS interface abstraction to emulate multiple levels of performance on a system that only supports basic run-fast and idle modes of operation. The DVS emulation is performed through a PWM-style power request on the IECPWRREQ output. The PWM duty cycle for the output depends on the current performance target specified by the IEM software.


In this mode of operation, the processor only executes at maximum 100% or minimum 0% performance levels. Consequently the only requirement of the DCG is to provide these performance levels for the processor.

This mode has a number of advantages and disadvantages as shown in Table 2.15.

Table 2.15. IEC DVS Emulation advantages and disadvantages

Simple SoC design-flow, Static Timing Analysis (STA) and verification at maximum performanceEnergy savings less than run-slow/idle
Fits switched leakage management power domainsNo forward progress until VDD fully ramped
Average power consumption is reducedProcessor executes at 100%-0% performance levels
-PWM-style power request approach

The following subsections describe:

PWM frame period

Each PWM frame is built from eight time slots. The time for each slot is programmable, and must be tuned by the software depending on the ramp and decay times for the voltage to go between maximum and minimum voltages. On reset, the time slots are set to 100μs. The length of each time slot is controlled by the value programmed in the IECDVSEMSTR Register and the IECDVSEMCLKEN input signal.

Figure 2.8 shows an example of three different PWM frames.

Figure 2.8. Example PWM frames

Example PWM frames

The sequence of events is as follows:

  1. Frame 1 has a duty cycle of 100% because the performance requested at that time by the IEM software is 100%. All the slots in Frame 1 are HIGH, this is known as the mark period. None of the slots are LOW, this is known as the space period.

  2. Frame k has a duty cycle of 50% because the performance requested at that time by the IEM software was 50%. In this case, half the slots of the frame are HIGH (the mark period) and half the slots are LOW (the space period).

  3. Frame n has a duty cycle of 75% because the performance requested at that time by the IEM software was 75%. In this case, six slots of the frame are HIGH (the mark period) and two slots are LOW (the space period).


Because eight slots are used in each frame, eight equally divided non-zero performance levels are supported in DVS emulation mode, each 12.5% higher than the previous level.

Frame duty cycle changes

The PWM duty cycle is changed when the IEM software programs a new performance level. At this point, the PWM frame is reset. Figure 2.9 shows an example of this happening.

In the figure you can see that frames 1 and 2 are both at 50%, the third frame starts at 50% as well but was not yet complete when the software programmed a new performance level (in slot3). The framing was reset at this point, and frame 4 started and the duty cycle was the new performance level of 75%. Frame 5 also had a 75% duty cycle.

Figure 2.9. Duty cycles changes in frames

Duty cycles changes in frames

Example DVS emulation

Figure 2.10 shows the sequence of events that occur when the software programs a new performance target and also how the IEC interacts with the processor to transition between sleep and wake-up. If for example the IEM software has requested a 50% performance level, in this situation, from Figure 2.10, you can see that at the end of the mark period, the IEC asserts the IECCPUSLPINT interrupt.

When the processor sees this interrupt, it is expected to save state as appropriate, flush its write buffers, clear the IECCPUSLPINT interrupt and execute the WFI command when the IECCPUSLPINT output has been cleared. The execution of this command causes the STANDBYWFI output from the processor to be asserted.

The STANDBYWFI output from the ARM processor must be connected to the IECCPUWFIACK input of the IEC. When the IEC detects a high level on this input, it de-asserts the IECPWRREQ output.


The IECCPUSLPINT interrupt can be cleared by writing a 1 to the corresponding bit in the IECICR Register.

At the end of the frame, the IEC asserts IECCPUWUINT to wake-up the processor and also requests power. The clock for the processor is not re-started by the DCG until a 1 is detected on IECCRNTDVCIDX, that is, until the power is available and stable. When the processor has woken up, IECCPUWFIACK is deasserted and it clears IECCPUWUINT.


A new frame starts when the power is requested through the IECPWRREQ output. Therefore, some of the frame is used up while the voltage for the processor is ramping up to the maximum level.

Figure 2.10. Simple example of DVS emulation

Simple example of DVS emulation

DVS emulation and IECMAXPERF assertion

Figure 2.11 shows the sequence of events when a maximum performance condition is triggered and how the IEC behaves in this situation. This figure shows that when IECMAXPERF is asserted, the system is at 50% performance level but is in a sleep state. That is, the voltage to the processor is at the retention level, this is the minimum level to enable the system to function. The assertion of IECMAXPERF has the following effect:

  • the current frame is terminated

  • IECPWRREQ is asserted by the IEC

  • the performance level is set to maximum

  • IECCPUWUINT is asserted.

When the voltage reaches the full level IECCRNTDVCIDX[7] is 1, the processor clock is enabled by the DCG, the processor clears IECCPUWUINT, services the maximum performance condition and clears IECMAXPERF and carries on doing more work. When IECMAXPERF is cleared, the IEC starts a new frame at the previously programmed performance level of 50%.

Figure 2.11. DVS emulation and IECMAXPERF

DVS emulation and IECMAXPERF
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