3.3.20. DPM Channel 1 Low Register

The IECDPM1LO Register enables you to read the current count in the low 32 bits of channel 1 of the DPM. It is a read-only register. When read it returns the current count of the low 32 bits of channel 1 of the DPM. The read also causes the high 32 bits of channel 1 to be captured. These high 32 bits are read through the IECDPM1HI Register.

Note

To read all 64 bits of channel 1 of the DPM, you must read the IECDPM1LO Register followed by a read of the IECDPM1HI Register. If you fail to follow this sequence then this results in an incorrect count for channel 1 when read.

Table 3.22 lists the register bit assignments.

Table 3.22. IECDPM1LO Register bit assignments

BitsNameDescription
[31:0]IECDPM1LOLow 32-bits of DPM channel 1. The reset value is 0x00000000.
Copyright © 2003, 2008 ARM Limited. All rights reserved.ARM DDI 0304C
Non-Confidential