IECDPMCR is a read and write register. A number of commands can be issued for each of the channels by the IEM software.
Figure 3.12 shows the bit assignments.
Table 3.18 lists the register bit assignments.
Table 3.18. IECDPMCR Register bit assignments
| Bits | Name | Description |
|---|---|---|
| [31:12] | Reserved | Reserved, read undefined, do not modify. |
| [11:8] | DPMCH3CMD | DPM Channel 3 command. |
| [7:4] | DPMCH2CMD | DPM Channel 2 command. |
| [3:0] | DPMCH1CMD | DPM Channel 1 command. |
The commands and their encoding for each of the channels are shown in Table 3.19.
Table 3.19. DPMCHxCMD encoding bit assignments
| DPMCHxCMD[1] | Command | Description |
|---|---|---|
| b’0000 | Freeze | The channel is frozen and stops accumulating. This is also the reset value. |
| b’0001 | Reset | The channel is reset to zero. |
| b’0010 | Accumulate | The channel starts accumulating. |
| b’0011 | Reserved | - |
| b’01xx[2] | Reserved | - |
| b’1xxx[2] | Reserved | - |
[1] The x indicates that the value applies to DPMCH1CMD, DPMCH2CMD, or DPMCH3CMD. [2] x is an ignored bit | ||
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