3.3.19. DPM Channel 3 Rate Register

The IECDPM3RATE Register controls the rate that channel 3 of the DPM accumulates. It is a read and write register. The rate is an 8-bit fractional value, that is, it is a fraction of the maximum performance. The format of the rate is identical to the format of the IECDPCTGTPERF Register, that is, it has an inherent binary point.

Figure 3.14 shows the bit assignments for this register.

Figure 3.14. IECDPM3RATE Register bit assignments

IECDPM3RATE Register bit assignments

Table 3.21 lists the register bit assignments.

Table 3.21. IECDPM3RATE Register bit assignments

[31:8]ReservedReserved, read undefined, do not modify.
[7:0]DPMCH3RATEThe fractional rate that DPM channel 3 counts. The reset value of this register is 0x80, that is, 100%.
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