3.3.8. Interrupt Clear Register

IECICR is a write-only register. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.

Figure 3.8 shows the bit assignments for this register.

Figure 3.8. IECICR Register bit assignments

IECICR Register bit assignments

Table 3.9 lists the register bit assignments.

Table 3.9. IECICR Register bit assignments

BitsNameDescription
[31:2]ReservedReserved, read undefined, do not modify
[1]CPU Sleep Interrupt Clear (CSIC)Clears the IECCPUSLPINT interrupt. The reset value is 0.
[0]CPU Wake-up Interrupt Clear (CWIC)Clears the IECCPUWUINT interrupt. The reset value is 0.
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