3.3.21. DPM Channel 1 High Register
The IECDPM1HI Register enables you to read the current count
in the high 32-bits of channel 1 of the DPM. It is a read only register.
When read it returns the previously captured count of the high 32
bits of channel 1 of the DPM. This count is captured when you read
the low 32 bits of channel 1.
Note
To read all 64 bits of channel 1 of the DPM, you must read
the IECDPM1LO Register followed by a read of the IECDPM1HI Register.
If you fail to follow this sequence then this results in an incorrect
count for channel 1 when read.
Table 3.23 lists
the register bit assignments.
Table 3.23. IECDPM1HI Register bit assignments
| Bits | Name | Description |
|---|
| [31:0] | IECDPM1HI | High 32-bits of DPM channel 1. The reset value
is 0x00000000. |
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