4.3.1. Integration Test Control Register

IECITCR is a read and write register. This general test register controls the operation of the IEC under test conditions. Figure 4.1 shows the register bit assignments.

Figure 4.1. IECITCR Register bit assignments

IECITCR Register bit assignments

Table 4.2 lists the register bit assignments.

Table 4.2. IECITCR Register bit assignments

BitNameDescription
[31:3]-Reserved. Unpredictable when read. Should be written as zero.
[2]DPM Counter Test Enable or disable test mode for all DPM counters. 0=DPM counter test mode disabled, also the reset value. 1=DPM counter test mode enabled. When this bit is set, the 64-bit DPM counters are split up into eight separate 8-bit counters, each accumulate by the CPU or programmed rate. This reduces the testing time required to ensure that all bits of the counters toggle correctly.
[1]DVS Emulation Slot Counter TestEnable or disable test mode for the bus V slotcounter. 0=DVS emulation slot counter test mode disabled, also reset value. 1=DVS emulation slot counter test mode enabled. When this bit is set, the 10-bit DVS emulation slot timing counter is split up into two 5-bit counters, each decrement separately. This reduces the testing time required to ensure that all bits of the counters toggle correctly.
[0]ITENIntegration test enable. When this bit is set to 1, the IEC is put into integration test mode. When 0, the IEC is in normal operating mode. The reset value is 0.
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