| Copyright © 2003, 2008 ARM Limited. All rights reserved. | ARM DDI 0304C |
| Non-Confidential | |
 PDF version | |
| Home > Programmer’s Model for Test > Test registers |
| |||
| Home > Programmer’s Model for Test > Test registers | |||
The IEC test registers are memory mapped as shown in Table 4.1 summarizes the IEC test registers in base offset order.
Table 4.1. Integration test registers
| Name | Base offset | Type | Reset nPOR | Description |
|---|---|---|---|---|
| IECITCR | 0xF00 | R/W | 0x0 | Integration Test Control Register. |
0xF04-0xF0F | - | - | Reserved, read undefined, do not modify. | |
| IECITIP1 | 0xF10 | R/W | 0x00 | Integration Test Input Read or Set Register 1. |
| IECITIP2 | 0xF14 | R/W | 0x0 | Integration Test Input Read or Set Register 2. |
| IECITIP3 | 0xF18 | R/W | 0x00 | Integration Test Input Read or Set Register 3. |
0xF14-0xF1F | - | 0x00 | Reserved, read undefined, do not modify. | |
| IECITOP1 | 0xF20 | R/W | 0x0 | Integration Test Output Read or Set Register 1. |
| IECITOP2 | 0xF24 | R/W | 0x00 | Integration Test Output Read or Set Register 2. |
| IECITOP3 | 0xF28 | R/W | 0x00 | Integration Test Output Read or Set Register 3. |
Test registers must not be accessed during normal mode of operation.
| Copyright © 2003, 2008 ARM Limited. All rights reserved. | ARM DDI 0304C |
| Non-Confidential | |
| PDF version | |
| Home > Programmer’s Model for Test > Test registers |