4.3. Test registers

The IEC test registers are memory mapped as shown in Table 4.1 summarizes the IEC test registers in base offset order.

Table 4.1. Integration test registers

NameBase offsetType

Reset

nPOR

Description
IECITCR0xF00R/W0x0Integration Test Control Register.
 0xF04-0xF0F--Reserved, read undefined, do not modify.
IECITIP10xF10R/W0x00Integration Test Input Read or Set Register 1.
IECITIP20xF14R/W0x0Integration Test Input Read or Set Register 2.
IECITIP30xF18R/W0x00Integration Test Input Read or Set Register 3.
 0xF14-0xF1F-0x00Reserved, read undefined, do not modify.
IECITOP10xF20R/W0x0Integration Test Output Read or Set Register 1.
IECITOP20xF24R/W0x00Integration Test Output Read or Set Register 2.
IECITOP30xF28R/W0x00Integration Test Output Read or Set Register 3.

Note

Test registers must not be accessed during normal mode of operation.

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