4.3.7. Integration Test Output Read or Set Register 3

IECITOP3 is a read and write register. In integration test mode, it enables outputs to be both written to and read from.

Figure 4.7 shows the bit assignments for the register.

Figure 4.7. IECITOP3 Register 3 bit assignments

IECITOP3 Register 3 bit assignments

Table 4.8 lists the register bit assignments.

Table 4.8. IECITOP3 Register bit assignments

BitNameDescription
[31:8]-Reserved, read undefined, do not modify.
[7:0]IECTGTDVCIDXIntra-chip outputs. Writes to these bits set the value to be driven onto the IECTGTDVCIDX[7:0] outputs in integration test mode. Reads return the value of IECTGTDVCIDX[7:0] at the output of the test multiplexer. The reset value is 0x00.
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