2.2.1. Performance level programming

The performance is expressed as the fraction of the maximum frequency required to ensure that the programming interface is portable and scalable across designs as they migrate with technology and product evolution. The primary interface for the IEM software is an implementation-independent programming mechanism to set the target performance level. An 8-bit fractional programming interface is provided to support up to 129 levels. Thirty-three levels are supported in this version of the IEC.

Note

Only 33 of the 129 levels are supported in this version of the IEC. The lowest two bits are discarded in hardware.

The IECDPCTGTPERF Register must be used to set this performance level. The format for programmable bits of the IECDPCTGTPERF Register has an inherent binary point in it. This is as listed in columns one and two of Table 2.1.

Table 2.1. Fractional performance map

IECDPCTGTPERF[7:0]Fractional(decimal)%Performance level
Programmed bit valueFractional bit value  
b’1xxxxxxx[1]RESERVEDRESERVED--
b’10000000b’1.00000xx1.00000100.0%32
b’011111xxb’0.11111xx0.9687596.9%31
b’011110xxb’0.11110xx0.9375093.8%30
b’011101xxb’0.11101xx0.9062590.6%29
b’011100xxb’0.11100xx0.8750087.5%28
b’011011xxb’0.11011xx0.8437584.4%27
b’011010xxb’0.11010xx0.8125081.3%26
b’011001xxb’0.11001xx0.7812578.1%25
b’011000xxb’0.11000xx0.7500075.0%24
b’010111xxb’0.10111xx0.7187571.9%23
b’010110xxb’0.10110xx0.6875068.8%22
b’010101xxb’0.10101xx0.6562565.6%21
b’010100xxb’0.10100xx0.6250062.5%20
b’010011xxb’0.10011xx0.5937559.4%19
b’010010xxb’0.10010xx0.5625056.3%18
b’010001xxb’0.10001xx0.5312553.1%17
b’010000xxb’0.10000xx0.5000050.0%16
b’001111xxb’0.01111xx0.4687546.9%15
b’001110xxb’0.01110xx0.4375043.8%14
b’001101xxb’0.01101xx0.40062540.6%13
b’001100xxb’0.01100xx0.3750037.5%12
b’001011xxb’0.01011xx0.3437534.4%11
b’001010xxb’0.01010xx0.3125031.3%10
b’001001xxb’0.01001xx0.2812528.1%9
b’001000xxb’0.01000xx0.2500025.0%8
b’000111xxb’0.00111xx0.2187521.9%7
b’000110xxb’0.00110xx0.1875018.8%6
b’000101xxb’0.00101xx0.1562515.6%5
b’000100xxb’0.00100xx0.1250012.5%4
b’000011xxb’0.00011xx0.093759.4%3
b’000010xxb’0.00010xx0.062506.3%2
b’000001xxb’0.00001xx0.031253.1%1
b’00000000b’0.00000000.000000.0%0

[1] x is an ignored bit.

Minimum performance levels required

The system-specific DCG is rarely able to generate all of the 33 possible performance levels explicitly so the requested performance level is quantized by rounding up to the next highest supported performance level. There is however a minimum requirement on the basic performance levels that the DCG must support. These are:

  • the maximum value (level 32) of 100%

  • the idle or clock-stopped case (level 0), that is 0%.

Note

See Performance quantization for more details.

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