The IEC interfaces to two on-chip components to set the target performance level and getting the current performance level, see also About the Intelligent Energy Manager. These are:
the DCG
the DVC.
The interfaces to both the DCG and DVC pass index values to and from the IEC to indicate current and target performance levels. Both the DCG and DVC blocks can be in different clock domains to the IEC and consequently any coding of these interfaces must be robust for asynchronous clock domains, that is, support a clean synchronization across the clock domains. In addition, the coding is defined to support easy extension for multiprocessor systems.
A thermometer coded interface, for example see Table 2.11, is chosen to indicate the indexes for the target and current performance interfacing to both the DCG and the DVC. The following signals are all coded using this scheme:
IECTGTDCGIDX
IECCRNTDCGIDX
IECTGTDVCIDX
IECCRNTDVCIDX.
This coding scheme enables single-ended signaling, without a requirement for an acknowledge, across asynchronous clock domains. There is a best level implicit acknowledge in the scheme. The following subsections describe the coding schemes:
The IEC interfaces support a maximum of eight non-zero performance levels, that is, performance levels 0 to 8 are supported. Table 2.11 shows the target performance levels that are coded in 8-bit buses.
Table 2.11. Target index coding for DVC and DCG
| DCG and DVC target index | Code | Note |
|---|---|---|
| 8 | 8'b11111111 | Performance level 8 select (maximum level) |
| 7 | 8'b01111111 | Performance level 7 select |
| 6 | 8'b00111111 | Performance level 6 select |
| 5 | 8'b00011111 | Performance level 5 select |
| 4 | 8'b00001111 | Performance level 4 select |
| 3 | 8'b00000111 | Performance level 3 select |
| 2 | 8'b00000011 | Performance level 2 select |
| 1 | 8'b00000001 | Performance level 1 select (minimum level) |
| 0 | 8'b00000000 | Retention level (clock stopped) |
From analyzing Table 2.11, you can see that, for a maximum performance level index, all bits are set to 1. Stepping through each performance level, the most significant bit from the previous performance level is set to zero. To decode the current performance level, the most significant bit that is set to 1 determines the performance level.
Note
When bit 0 is set to zero, it signifies 0% performance level. That is, you can stop the clock if required, and you can lower the voltage to the processor to the retention level.
This interface supports future extension to cope with clocks derived from more than one PLL. This is done by expanding the number of bits used for the DCG and DVC target index.
Table 2.12 shows the extensible coding scheme that are coded in 8-bit buses. This is used to determine the valid current level of performance.
Table 2.12. Current index coding for DVC and DCG
| DCG and DVC current index | Code | Note |
|---|---|---|
| 8 | 8'b1xxxxxxx | Performance level 8 valid (MAX level) |
| 7 | 8'b01xxxxxx | Performance level 7 valid |
| 6 | 8'b001xxxxx | Performance level 6 valid |
| 5 | 8'b0001xxxx | Performance level 5 valid |
| 4 | 8'b00001xxx | Performance level 4 valid |
| 3 | 8'b000001xx | Performance level 3 valid |
| 2 | 8'b0000001x | Performance level 2 valid |
| 1 | 8'b00000001 | Performance level 1 valid (MIN level) |
| 0 | 8'b00000000 | Retention level (Clock stopped) |
Table 2.13 shows that the IEC interfaces support eight non-zero index levels. Both the current and target performance level indexes are coded in 8-bit buses. If your system only implements five performance levels, that is, four non-zero levels, then you must connect the most significant bits to and from the IEC for the following signals:
IECTGTDVCIDX
IECCRNTDVCIDX
IECTGTDCGIDX
IECCRNTDCGIDX.
Note
You must tie the unused bits in the IECCRNTDVCIDX and IECCRNTDCGIDX signals to 1.
Table 2.13. Example performance level index coding
| Performance level | [7] | [6] | [5] | [4] | [3] | [2] | [1] | [0] |
|---|---|---|---|---|---|---|---|---|
| Performance level 8 (maximum) | 1 | 1 | 1 | 1 | x | x | x | x |
| Performance level 7 | 0 | 1 | 1 | 1 | x | x | x | x |
| Performance level 6 | 0 | 0 | 1 | 1 | x | x | x | x |
| Performance level 5 (minimum) | 0 | 0 | 0 | 1 | x | x | x | x |
| Performance level 4/3/2/1/0 (clocks stopped) | 0 | 0 | 0 | 0 | x | x | x | x |
Note
Bits [3:0] are treated as don’t care. In Table 2.13 only performance levels 5-8 are used.
For the maximum performance level index, bits [7:4] are set to 1.
The minimum performance level is when bit 4 is 1 while bits [7:5] are 0.
When bits [7:4] are 0, the clocks can be stopped.
The coding scheme enables performance requirement optimization as long as the DVC block provides the encoded index information to reflect the availability of stable voltage for each of the performance levels. For example, if the current performance is at a low level and the target performance level is set to maximum. The sequence of events is:
IEC requests
maximum performance to DVC
maximum frequency to DCG
DVC commands PSU to go to maximum voltage
DVC monitors feedback from PSU to determine when the next highest supported clock frequency can be changed to, as
Vddrises toVmax, then:DVC indicates to DCG to move to a new frequency.
All intermediate supported frequency points can be used, and as a result as much work as possible can be achieved on the way to
Vmax.
The sequence of events is depicted in Figure 2.4. You can see that the IECCRNTDVCIDX values change as each intermediate stable voltage is reached. Figure 2.4 also shows how the IECCRNTDVCIDX changes when the voltage is lowered, 100% to 50% transition, and also what happens when a subsequent increase in performance is requested, 50% to 75% transition.
The IECCRNTDVCIDX output from the DVC is also used by the DCG to supply the appropriate clock at each index position.
The DCG uses the same encoding on the IECCRNTDCGIDX output and Table 2.14 shows an example of clock ready coding where the DCG indicates the availability of clean stable clocks by setting the appropriate bit to HIGH. This shows the case where the DCG only supports four performance levels.
The thermometer coding schemes support the basic operations required to handle performance level comparisons and the determination of maximum or minimum levels in a multiprocessor system. In such a system, it is expected that there is one IEC per processor:
The logical OR of two levels results in the higher of the two levels. For example, in a 2-processor system, the DVC index can be worked out using:
IECTGTDVCIDX1[7:0] | IECTGTDVCIDX2[7:0]
That is, the highest voltage of all requests is selected.
The logical AND of two levels results in the lower of the two levels. For example, in a 2-processor system, to ensure that the lower processor clock is selected before starting to reduce voltage the following calculation can be performed:
IECTGTDCGIDX1[7:0] & IECTGTDCGIDX2[7:0]
That is, the lowest performance level of all requests is selected.
Because each bit can be synchronized safely and independently, this simple coding also supports efficient clock selection.
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