2.2.4. Maximum performance request IECMAXPERF signal

The IEC provides a mechanism for the hardware to respond to critical and unpredicted high-priority events. This is through a maskable IECMAXPERF input. It provides a hardware mechanism to override any software programmed performance level. You can assert this signal to force the IEC to request maximum performance from the DCG, DVC. This results in the maximum frequency and voltage in the shortest time.

This signal is level sensitive and must be de-asserted when the critical requirements have been met. The signal is treated as an asynchronous input and is internally synchronized.

A simple usage of this could be to force maximum performance to service interrupts or scheduled real-time requirements.

Figure 2.5 shows how the IEC requests maximum performance when IECMAXPERF is asserted.


  • when IECMAXPERF is cleared, the IEC then requests the previously programmed software performance level.

  • because of the time taken for voltage to ramp, and the incremental performance increases (see Performance requirement optimization), it is possible that the condition causing maximum performance request, might be over before Vmax is reached.

  • the IECMAXPERF input can be used by the system to wake-up the processor when it is in 0% performance level state.

Figure 2.5. Requesting maximum performance when IECMAXPERF is asserted

Requesting maximum performance when IECMAXPERF is asserted

Simple example usage of IECMAXPERF

In a SoC, you can use a number of different conditions to trigger the maximum performance request. The simplest usage of this is to request the maximum performance whenever an interrupt request is received. That is, IECMAXPERF could be tied to the output of the SoC interrupt controller.

For example, if the SoC has a PrimeCell Vector Interrupt Controller (VIC), then you can tie a logical OR of the inverse of the nIRQ and nFIQ outputs from the VIC to the IECMAXPERF input of the IEC. The inversion is required because the IECMAXPERF input is active HIGH.


You must also connect the nIRQ and nFIQ outputs from the PrimeCell VIC to the nIRQ and nFIQ inputs of the ARM processor.

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