2.2.5. Synchronization mode handshaking signals

The IEC provides support for synchronization mode handshaking with synchronous and asynchronous bridges used in an asynchronous design based around the AMBA specification.When the system is running at the 100% performance level, the master and slave clocks to the synchronous and asynchronous bridges should be synchronous for optimal performance. At all other times the master and slave clocks are asynchronous because of unpredictable clock tree latencies in these performance levels.When the system and processor clocks are synchronous, the synchronous and asynchronous bridges can bypass synchronization logic to reduce the transfer latency. To do this, a handshaking mechanism is used to control entry to and exit from synchronous mode.

The request and acknowledge assertion and deassertion are shown in Figure 2.6.

Figure 2.6. IEC and Synchronous/Asynchronous handshaking timing

IEC and Synchronous/Asynchronous handshaking timing

When the synchronous and asynchronous bridges start to switch modes, it must be able to complete the change. That is, when the IEC has driven the IEMSYNCMODEREQ output to a new value it does not change again until the IECSYNCMODEACK input indicates the synchronous and asynchronous bridges have completed the mode change.

For example, if during a transition to synchronous mode the performance level is reduced from 100%, the IEC with the synchronous and asynchronous bridges complete the change to synchronous mode before starting to change back to asynchronous mode.

Any transitions between performance levels lower than 100% do not require interaction with the synchronous and asynchronous bridges, because it remains in asynchronous mode. The handshaking is only required for entry to or exit from the 100% performance level.

You can connect up multiple bridges at the same time. The request from IEC to bridges can be connected directly to all bridges, but acknowledges from bridges must be ANDed together before being passed to the IEC, ensuring that the IEC does not change mode until all bridges have changed mode.

Note

Synchronizer handshaking is not expected to be required in a DVS emulation system, as only a single clock frequency is used by the processor, rather than multiple synchronous and asynchronous frequencies. Therefore, synchronous and asynchronous bridge handshaking must be disabled when DVS emulation is used.

Asynchronous to synchronous mode

The following steps are performed when the system is running in asynchronous mode and the 100% performance level is requested:

  1. The software programs the performance level to 100%.

  2. The IEC drives the DVC and DCG target levels to 100%.

  3. When the voltage has reached the maximum level, the processor clock is set to the maximum frequency and the DCG indicates the current performance level is 100%. The DCG also ensures that the system and processor clocks are synchronous.

  4. The IEC asserts IECSYNCMODEREQ now that the processor can be run synchronized with the rest of the system.

  5. The synchronous and asynchronous bridge flushes its FIFOs, switches into synchronous mode and asserts IECSYNCMODEACK.

Synchronous to asynchronous

The following steps are performed when the system is running at the 100% performance level in synchronous mode and a reduction in performance is requested:

  1. The software programs the performance level less than100%.

  2. The IEC deasserts IECSYNCMODEREQ.

  3. The synchronous and asynchronous bridge switches into asynchronous mode and deasserts IECSYNCMODEACK.

  4. The IEC drives the DVC and DCG target levels to the new value.

  5. The DCG generates the slower asynchronous clock for the processor, and the DVC requests a lower voltage from the PSU after the DCG has reduced the clock frequency.

Note

If you do not use this handshaking then you must tie the IECSYNCMODEACK input HIGH.

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