Intelligent Energy Controller Technical Reference ManualRevision: r0p1
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Intelligent Energy Controller Technical Reference Manual

Revision: r0p1

Copyright © 2003, 2008 ARM Limited. All rights reserved.

Proprietary notices

Table of Contents

Preface
About this manual
Product revision status
Intended audience
Using this manual
Conventions
Further reading
Feedback
Feedback on this product
Feedback on this manual
1. Introduction
1.1. About the Intelligent Energy Manager
1.1.1. Dynamic Clock Generator
1.1.2. Hardware Performance Monitor
1.1.3. Dynamic Voltage Controller
1.1.4. Intelligent Energy Controller
1.1.5. PSU
1.1.6. IEM software
1.2. Typical system configuration
1.2.1. Open loop voltage control
1.2.2. Closed loop voltage control
1.3. Product Revisions
2. Functional Overview
2.1. Functional overview
2.1.1. APB interface
2.1.2. Configuration interface
2.1.3. Dynamic Performance Controller (DPC)
2.1.4. Dynamic Performance Monitor (DPM)
2.1.5. DVS emulation
2.1.6. IEC clock
2.1.7. IEC reset
2.2. Functional operation
2.2.1. Performance level programming
2.2.2. Configuration setting
2.2.3. Target index and current index
2.2.4. Maximum performance request IECMAXPERF signal
2.2.5. Synchronization mode handshaking signals
2.2.6. Maskable interrupts
2.2.7. Acknowledgement of WaitForInterrupt signal
2.2.8. DPM channels
2.2.9. DVS emulation with PWM
2.2.10. IEC and software development support
2.2.11. IEC and SoC DFT
3. Programmer’s Model
3.1. About the programmer’s model
3.2. Summary of registers
3.3. Register descriptions
3.3.1. DPC Control Register
3.3.2. DVS Emulation Slot Time Register
3.3.3. DPC Target Performance Register
3.3.4. DPC Current Performance Register
3.3.5. Interrupt Mask Set and Clear Register
3.3.6. Raw Interrupt Status Register
3.3.7. Masked Interrupt Status Register
3.3.8. Interrupt Clear Register
3.3.9. Configured CPU Frequency Register
3.3.10. DPM Frequency Register
3.3.11. Configuration Fractional Index Map 00 Register
3.3.12. Configuration Fractional Index Map 32 Register
3.3.13. Configuration Fractional Index Map 64 Register
3.3.14. Configuration DVC Index Map Register
3.3.15. Configuration Performance Map 0 Register
3.3.16. Configuration Performance Map 4 Register
3.3.17. DPM Command Register
3.3.18. DPM Channel 2 Rate Register
3.3.19. DPM Channel 3 Rate Register
3.3.20. DPM Channel 1 Low Register
3.3.21. DPM Channel 1 High Register
3.3.22. DPM Channel 2 Low Register
3.3.23. DPM Channel 2 High Register
3.3.24. DPM Channel 3 Low Register
3.3.25. DPM Channel 3 High Register
3.3.26. Peripheral Identification Registers
3.3.27. IEC Identification Registers
4. Programmer’s Model for Test
4.1. IEC test harness overview
4.2. Scan testing
4.3. Test registers
4.3.1. Integration Test Control Register
4.3.2. Integration Test Input Read or Set Register 1
4.3.3. Integration Test Input Read or Set Register 2
4.3.4. Integration Test Input Read or Set Register 3
4.3.5. Integration Test Output Read or Set Register 1
4.3.6. Integration Test Output Read or Set Register 2
4.3.7. Integration Test Output Read or Set Register 3
A. Signal Descriptions
A.1. IEC signals
A.1.1. Clock and resets
A.1.2. APB Slave interface
A.1.3. Interrupts
A.1.4. Request and acknowledge
A.1.5. DVC control and status
A.1.6. DCG control and status
A.1.7. DPM channel enable
A.1.8. Configuration
A.1.9. DVS emulation
A.1.10. Synchronization mode handshaking
A.1.11. DFT interface
B. Revisions
Glossary

List of Figures

1. Key to timing diagram conventions
1.1. Intelligent Energy Manager solution
1.2. IEM on-chip components
1.3. An example IEM enabled system with open loop voltage control
1.4. An example IEM-enabled system with closed loop voltage control
2.1. IEC simplified block diagram
2.2. IEC performance level flow
2.3. IECCFGDCGIDXMAP example
2.4. DVS and performance requirement optimization
2.5. Requesting maximum performance when IECMAXPERF is asserted
2.6. IEC and Synchronous/Asynchronous handshaking timing
2.7. PCLK and IECDPMCLKEN relationship
2.8. Example PWM frames
2.9. Duty cycles changes in frames
2.10. Simple example of DVS emulation
2.11. DVS emulation and IECMAXPERF
3.1. IECDPCCR Register bit assignments
3.2. IECDVSEMSTR Register bit assignments
3.3. IECDPCTGTPERF Register bit assignments
3.4. IECDPCCRNTPERF Register bit assignments
3.5. IECIMSC Register bit assignments
3.6. IECRIS Register bit assignments
3.7. IECMIS Register bit assignments
3.8. IECICR Register bit assignments
3.9. IECCFGCPUFREQ Register bit assignments
3.10. IECDPMFREQ Register bit assignments
3.11. IECCFGDVCIDXMAP Register bit assignments
3.12. IECDPMCR Register bit assignments
3.13. IECDPM2RATE Register bit assignments
3.14. IECDPM3RATE Register bit assignments
3.15. Peripheral Identification Register bit assignments, IECPeriphID0-3
3.16. Peripheral Identification Register bit assignments, IECPeriphID4-7
3.17. Identification Register bit assignments
4.1. IECITCR Register bit assignments
4.2. IECITIP1 Register 1 bit assignments
4.3. IECITIP2 Register 2 bit assignments
4.4. IECITIP3 Register 3 bit assignments
4.5. IECITOP1 Register 1 bit assignments
4.6. IECITOP2 Register 2 bit assignments
4.7. IECITOP3 Register 3 bit assignments

List of Tables

2.1. Fractional performance map
2.2. IECCFGDCGIDXMAP signal 3-bit slicing and performance level
2.3. IECCFGDCGIDXMAP slice coding
2.4. IECCFGDCGPERFMAP example
2.5. IECCFGDVCIDXMAP signal bits and DCG slice index level
2.6. IECCFGDVCIDXMAP slice coding
2.7. IECCFGDVCIDXMAP example 2
2.8. IECCFGDVCIDXMAP example 1
2.9. IECCFGFREQCPU examples
2.10. IECCFGFREQDPM examples
2.11. Target index coding for DVC and DCG
2.12. Current index coding for DVC and DCG
2.13. Example performance level index coding
2.14. Example clock ready coding
2.15. IEC DVS Emulation advantages and disadvantages
3.1. Summary of registers
3.2. IECDPCCR Register bit assignments
3.3. IECDVSEMSTR Register bit assignments
3.4. IECDPCTGTPERF Register bit assignments
3.5. IECDPCCRNTPERF Register bit assignments
3.6. IECIMSC Register bit assignments
3.7. IECRIS Register bit assignments
3.8. IECMIS Register bit assignments
3.9. IECICR Register bit assignments
3.10. IECCFGCPUFREQ Register bit assignments
3.11. IECDPMFREQ Register bit assignments
3.12. IECCFGDCGIDXMAP00 Register bit assignments
3.13. IECCFGDCGIDXMAP32 Register bit assignments
3.14. IECCFGDCGIDXMAP64 Register bit assignments
3.15. IECCFGDVCIDXMAP Register bit assignments
3.16. IECCFGDCGPERFMAP0 Register bit assignments
3.17. IECFGDCGPERFMAP4 Register bit assignments
3.18. IECDPMCR Register bit assignments
3.19. DPMCHxCMD encoding bit assignments
3.20. IECDPM2RATE Register bit assignments
3.21. IECDPM3RATE Register bit assignments
3.22. IECDPM1LO Register bit assignments
3.23. IECDPM1HI Register bit assignments
3.24. IECDPM2LO Register bit assignments
3.25. IECDPM2HI Register bit assignments
3.26. IECDPM3LO Register bit assignments
3.27. IECDPM3HI Register bit assignments
3.28. Peripheral Identification Register options, IECPeriphID0-3
3.29. Peripheral Identification Register options, IECPeriphID4-7
3.30. IECPeriphID0 Register bit assignments
3.31. IECPeriphID1 Register bit assignments
3.32. IECPeripID2 Register bit assignments
3.33. IECPeriphID3 Register bit assignments
3.34. IECPeriphID4 Register bit assignments
3.35. IECPeriphID5 Register bit assignments
3.36. IECPeriphID6 Register bit assignments
3.37. IECPeriphID7 Register bit assignments
3.38. IECID0 Register bit assignments
3.39. IECID1 Register bit assignments
3.40. IECID2 Register bit assignments
3.41. IECID3 Register bit assignments
4.1. Integration test registers
4.2. IECITCR Register bit assignments
4.3. IECITIP1 Register 1 bit assignments
4.4. IECITIP2 Register 2 bit assignments
4.5. IECITIP3 Register 3 bit assignments
4.6. IECITOP1 Register 1 bit assignments
4.7. IECITOP2 Register 2 bit assignments
4.8. IECITOP3 Register bit assignments
A.1. Clock and reset signals
A.2. APB interface signal
A.3. Interrupt signals
A.4. Request and acknowledge signals
A.5. DVC control and status signals
A.6. DCG control and status signals
A.7. DPM channel enable signal
A.8. Configuration interface signals
A.9. DVS emulation signals
A.10. Synchronization mode handshaking signals
A.11. DFT interface signals
B.1. Differences between issue B and issue C

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarks owned by ARM Limited, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A17 December 2003First release for r0p0
Revision B26 July 2005Updates for r0p1
Revision C04 June 2008Second release for r0p1
Copyright © 2003, 2008 ARM Limited. All rights reserved.ARM DDI 0304C
Non-Confidential
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