3.1. About the programmer’s model

The following applies to the IPCM registers:


Only Mailbox?0 and the Interrupt Status registers for Interrupt0 are fully expanded for clarity. However, Mailboxes 1-31 at offsets 0x040-0x7FC, and Interrupt 1-31 at offsets 0x808-0x8FC also exist, depending on your configuration.

Because of the highly configurable nature of the IPCM, all the registers shown here might not be available in every configuration of the IPCM. Any writes to unavailable registers are ignored and any reads of unavailable registers return 0x00000000.

MBOXNUM defines which Mailbox Registers are available. For example, when MBOXNUM is set to 1, only Mailbox0 Registers is available. When MBOXNUM is set to 32, all Mailbox Registers are available.

INTNUM defines the bit width of the IPCMxSOURCE, IPCMxDCLEAR, IPCMxDSET, IPCMxDSTATUS, IPCMxMCLEAR, IPCMxMSET, and IPCMxMSTATUS Registers. For example, when INTNUM is set to 1, the registers listed above are all only a single bit wide (bit?0). Setting INTNUM to 32 sets the registers to 32 bits wide.

Secondly, INTNUM defines which IPCMRISx and IPCMMISx registers are available. For example, when INTNUM is set to 1, only the IPCMRIS0 and IPCMMIS0 Registers are available. When INTNUM is set to 32, all IPCMRIS0 to IPCMRIS31 Registers and IPCMMIS0 to IPCMMIS31 registers are available.

Finally, INTNUM also defines which interrupt outputs are active. Although IPCMINT[31:0] is always 32 bits wide, INTNUM defines which bits can be set. For example, when INTNUM is set to 1, only IPCMINT[0] can be set. When INTNUM is set to 32, all IPCMINT[31:0] bits can be set.

DATANUM defines which IPCMxDATAn registers are available, where x is defined by MBOXNUM. Setting DATANUM to 0 means there are no IPCMxDATAn Registers available. Setting DATANUM to 1 means the IPCMxDATA0 Registers are available. Setting DATANUM to 7, means all IPCMxDATA0 to IPCMDATA6 Registers are available.

Figure 3.1 shows the IPCM register map.

Figure 3.1. IPCM register map

Figure 3.2 shows the register map for Mailbox0.

Figure 3.2. Mailbox0 register map

Figure 3.3 shows the register map for each Interrupt0.

Figure 3.3. Interrupt0 register map

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