2.3.4. Auto Link messaging from Core0 to Core1 using Mailbox0 and Mailbox1

In this example system, there are two cores and four mailboxes. Core0 is the source core and Core1 is the destination core. Core?0 uses Channel ID1 and Core1 uses Channel ID2. Core0 sets up Mailbox0 and Mailbox1 in Auto Link mode, and sends a message to Core1. Core1 responds to each interrupt separately and acknowledges both. Core0 only obtains an acknowledge interrupt when Core1 has finished with the final message. This example assumes that the IPCM has interrupts enabled and is not in integration test mode. Mailboxes 2-3 are inactive and Auto Acknowledge is disabled. Figure 2.11 shows the configuration.

Figure 2.11. Configuration, Auto Link messaging from Core0 to Core1 using Mailbox0 and Mailbox1

Figure 2.12 shows the messaging sequence.

Figure 2.12. Auto Link messaging from Core0 to Core1 using Mailbox0 and Mailbox1

In this example, the following sequence occurs:

  1. Core0 gains control of Mailbox0 and sets bit 0 in the IPCM0SOURCE Register.

  2. Core0 gains control of Mailbox1 and sets bit 0 in the IPCM1SOURCE Register.

  3. Core0 links Mailbox?0 to Mailbox1 by setting bit 1 in the IPCM0MODE Register.

  4. Core0 enables interrupts to Core0 and Core1 by setting bits 0 and 1 in the IPCM0MSTATUS Register.

  5. Core0 defines the destination core of Mailbox?0 by setting bit 1 in the IPCM0DSTATUS Register.

  6. Core0 programs the data payload of Mailbox?0 by setting the IPCM0DR0 Register to DA7A0000.

  7. Core0 enables interrupts to Core0 and Core1 by setting bits 0 and 1 in the IPCM1MSTATUS Register.

  8. Core0 defines the destination core of Mailbox1 by setting bit 1 in the IPCM1DSTATUS Register.

  9. Core0 programs the data payload of Mailbox1 by setting Data1 to DA7A1111.

  10. Core0 sets bit 1 in the IPCM0SEND Register to send the message in Mailbox0.

  11. Core1 reads the IPCMRIS1 Register and reads the data payload in Mailbox0.

  12. Core1 clears bit 0 and sets bit 1 in the IPCM0SEND Register to provide the Manual Acknowledge back to Core0.

    Note

    There is no acknowledge interrupt to Core?0.

  13. The message in Mailbox1 is automatically sent, triggered by bit 1 in the IPCM0SEND Register going HIGH and Auto Link mode being active.

  14. Core?1 reads the IPCMRIS1 Register and reads the data payload in Mailbox1.

  15. Core1 clears bit 0 and sets bit 1 in the IPCM1SEND Register to provide the Manual Acknowledge back to Core0.

    Note

    This sends the acknowledge interrupt to Core0.

  16. Core0 reads the IPCMRIS0 Register indicating that Mailbox1 has an acknowledge message. This indicates that the linked messages have all been sent. Core0 also reads the optional acknowledge data payload in Mailbox0.

  17. Core0 clears bit 1 in the IPCM0SEND Register.

  18. Core0 reads the optional acknowledge data payload in Core1.

  19. Core0 clears bit 1 in the IPCM1SEND Register.

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