3.3.9. Mailbox Send Registers

The read/write IPCMxSEND Registers send the message to either the source or destination cores.

The Mailbox Send Register bits can only be written to after the Mailbox Source Register is defined:


Setting both bits 0 and 1 is not valid and can give unpredictable results. Clearing any send bit clears the interrupt generated by that mailbox.

In Auto Acknowledge mode, when the Mailbox Destination Status Register changes from being non-zero to zero and the Mailbox Send Register currently contains 01, the mailbox automatically changes the register to 10, triggering the Auto Acknowledge interrupt back to the source core.

The Mailbox Send Registers are cleared when the Mailbox Source Register is cleared.

Figure 3.5 shows the register bit assignments.

Figure 3.5. IPCMxSEND Register bit assignments

Table 3.10 lists the register bit assignments.

Table 3.10. IPCMxSEND Register bit assignments


Read undefined. Write as zero.

[1:0]SendSend message: 00 = inactive 01 = send message to destination core(s) 10 = send message to source core 11 = invalid, unpredictable behavior
Copyright © 2003, 2004. ARM Limited. All rights reserved.ARM DDI 0306B