2.3.3. Messaging from Core0 to Cores 1, 2, and 3 using Auto Acknowledge

In this example system, there are four cores and four mailboxes:

Core0 is the source core and sends a message to three destination cores, 1, 2, and 3. This example assumes that the IPCM is not in integration test mode. Mailboxes 1-3 are inactive and Auto Link is disabled. Figure 2.9 shows the configuration.

Figure 2.9. Configuration, messaging from Core0 to Cores 1, 2, and 3 using Auto Acknowledge

Figure 2.10 shows the messaging sequence.

Figure 2.10. Messaging from Core0 to Cores 1, 2, and 3 using Auto Acknowledge

In this example, the following sequence occurs:

  1. Core0 gains control of Mailbox0 and identifies itself as the source core by setting bit 0 in the IPCM0SOURCE Register.

  2. Core0 sets Mailbox Mode Register bit 0 to put the mailbox into Auto Acknowledge mode.

  3. Core?0 enables interrupts to Core0, Core1, Core2, and Core3 by setting bits 0, 1, 2, and 3 in the IPCM0MSTATUS Register.

  4. Core0 defines the destination cores by setting bits 1, 2, and 3 in the IPCM0DSTATUS Register.

  5. Core0 programs the data payload, DA7A0000.

  6. Core0 sets bit 0 of the IPCM0SEND Register to send the interrupts to the destination cores.

  7. Core1 reads the IPCMRIS1 Register and reads the data payload.

  8. Core1 clears bit 1 in the IPCM0DSTATUS Register.

  9. Core3 reads the IPCMRIS3 Register and reads the data payload.

  10. Core3 clears bit 3 in the IPCM0DSTATUS Register.

  11. Core2 reads the IPCMRIS2 Register and reads the data payload.

  12. Core2 clears bit 2 in the IPCM0DSTATUS Register. As the final Mailbox Destination Register bit is cleared, the mailbox automatically detects this, clears Mailbox Send Register bit 0 and sets Mailbox Send Register bit 1 to provide the Auto Acknowledge back to the source core, Core?0. The data registers are not updated in Auto Acknowledge mode.

  13. Core0 reads Status0 and reads the data payload.

  14. Core?0 clears the interrupt and releases ownership of the mailbox by clearing the IPCM0SOURCE register, which in turn clears the IPCM0SEND and IPCM0DR0 Registers.

Note

If Core0 has another message to send, it can maintain ownership of the mailbox by keeping the IPCM0SOURCE Register set, and updating the IPCM0DSTATUS, IPCM0MODE, IPCM0MSTATUS, and IPCM0DR0 Registers with the new message at step 14.

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