3.3.11. Masked Interrupt Status Registers

The read-only IPCMMISx Registers contain the current mailbox status for every interrupt identified by the address encoding. This enables each core to read a single register to determine which mailbox caused the interrupt. For example, if Core?0 is mapped to Channel ID?0, it reads IPCMMIS0 to determine which mailboxes require attention.

Figure 3.6 shows how Mailbox?0 status is presented to Core?0 through the use of two status registers, IPCMMIS0 and IPCMRIS0.

Figure 3.6. Mailbox status

The Masked Interrupt Status Registers identify which mailbox triggered the interrupt. This value is the logical AND of the raw interrupt status with the Mailbox Mask Status Registers. All Masked Interrupt Status Register outputs are ORed together to form the IPCMINT[31:0] interrupt output bus.

Table 3.12 lists the register bit assignments.

Table 3.12. IPCMMISx Register bit assignments

[31:0]MaskIntStatMasked interrupt status
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