3.3.14. Peripheral Identification Registers

The IPCMPeriphID0-3 Registers are four 8-bit registers, that span address locations 0xFE0-0xFEC. You can conceptually treat the registers as a single 32-bit register. The read-only registers provide the following options of the peripheral:

PartNumber[11:0]

This is used to identify the peripheral. The product code 0x320 is used for the IPCM.

DesignerID[19:12]

This is the identification of the designer. ARM Limited is 0x41 (ASCII A).

Revision[23:20]

This is the revision number of the peripheral. The revision number starts from 0 and is revision dependent.

Configuration[31:24]

This is the configuration option of the peripheral. The configuration value is 0.

Figure 3.8 shows the register bit assignments.

Figure 3.8. Peripheral Identification Register bit assignments

Note

When you design a system memory map then you must remember that the register has a 4KB-memory footprint. All memory accesses to the peripheral identification registers must be 32-bit, using the LDR and STR instructions.

The Peripheral Identification Registers are described in the following subsections:

Peripheral Identification Register 0

The hard-coded IPCMPeriphID0 Register defines the reset value. Table 3.15 lists the bit assignments for the IPCMPeriphID0 Register.

Table 3.15. IPCMPeriphID0 Register bit assignments

Bits

Name

Description

[31:8]

-

Read undefined

[7:0]

PartNumber0

These bits read back as 0x20

Peripheral Identification Register 1

The hard-coded IPCMPeriphID1 Register defines the reset value. Table 3.16 lists the bit assignments for the IPCMPeriphID1 Register.

Table 3.16. IPCMPeriphID1 Register bit assignments

Bits

Name

Description

[31:8]

-

Read undefined

[7:4]

Designer0

These bits read back as 0x1

[3:0]

PartNumber1

These bits read back as 0x3

Peripheral Identification Register 2

The hard-coded IPCMPeriphID2 Register defines the reset value. Table 3.17 lists the bit assignments for the IPCMPeriphID2 Register.

Table 3.17. IPCMPeriphID2 Register bit assignments

Bits

Name

Description

[31:8]

-

Read undefined

[7:4]

Revision

These bits read back as 0x0

[3:0]

Designer1

These bits read back as 0x4

Peripheral Identification Register 3

The hard-coded IPCMDPeriphID3 Register defines the reset value. Table 3.18 lists the bit assignments for the IPCMPeriphID3 Register.

Table 3.18. IPCMPeriphID3 Register bit assignments

Bits

Name

Description

[31:8]

-

Read undefined

[7:0]

Configuration

These bits read back as 0x00

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