2.2.1. Basic operation

Figure 2.3 shows an example system in which the IPCM is integrated so that IPCMINT[0] is connected to the interrupt controller for Core0 and IPCMINT[1] is connected to the interrupt controller for Core1.

Figure 2.3. Basic operation

The IPCM operates as follows:

  1. Core0 has a message to send to Core1. Core0 claims the mailbox by setting bit 0 in the Mailbox Source Register. Core0 then sets bit 1 in the Mailbox Destination Register, enables the interrupts and programs the message into the Mailbox Data Registers. Finally, Core?0 sends the message by writing 01 to the Mailbox Send Register. This asserts the interrupt to Core1.

  2. When Core1 is interrupted, it reads the Masked Interrupt Status Register for IPCMINT[1] to determine which mailbox contains the message. Core1 reads the message in that mailbox, then clears the interrupt and asserts the acknowledge interrupt by writing 10 to the Mailbox Send Register.

  3. Core0 is interrupted with the acknowledge message, completing the operation. Core0 then decides whether to retain the mailbox to send another message or release the mailbox, freeing it up for other cores in the system to use it.

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