2.2.3. Using mailboxes

This section describes:

Defining source core

A core must obtain a mailbox to send a message. To do this the core writes one of its Channel IDs to the Mailbox Source Register and then reads the Mailbox Source Register back again to check whether the write was successful. The Mailbox Source Register must only contain a one-hot encoded value, that is, a single Channel ID. The software must ensure that only a one-hot encoded number is written to the Mailbox Source Register. You can only clear the Mailbox Source Register after it is programmed. Any writes other than 0x00000000 are ignored. This mechanism guarantees that only a single core has control of the mailbox at any one time.

A core gives up a mailbox, when it is no longer required, by clearing the Mailbox Source Register. Clearing the Mailbox Source Register also clears all the other registers in the mailbox. This guarantees that a mailbox is always cleared when it is newly allocated.

Defining destination core

The Mailbox Destination Register has separate Set and Clear write locations to enable you to set individual bits in the Mailbox Destination Register without using read-modify-write transfers. You can set a single bit in the Mailbox Destination Register by writing that bit to the Destination Set Register. This causes the hardware to OR that bit with the current Mailbox Destination Register value. Similarly, you can clear a single bit in the Mailbox Destination Register by writing that bit to the Destination Clear Register.

When the source core defines the mode of a mailbox, it defines which other cores are to receive the message by programming the OR of all the Channel IDs into the Mailbox Destination Register. If a core has more than one Channel ID only one is used per message. You can only write to the Mailbox Destination Register after the Mailbox Source Register is defined.

Using the Mailbox Mask Register

The Mailbox Mask Register uses separate Set and Clear registers for modification similar to the Mailbox Destination Register. The Mailbox Mask Register enables the interrupt outputs. To enable interrupts for a particular mailbox, a core writes its Channel ID to the Mask Set location. The interrupt for that mailbox can be masked out by writing the same Channel ID to the Mask Clear location. You can only write to the Mailbox Mask Register locations after the Mailbox Source Register is defined.

Using the Mailbox Send Register

A message is sent by setting bit 0 of the Mailbox Send Register. This triggers the interrupt to the destination core. Clearing this bit clears the interrupt to the destination core. The acknowledge message is sent to the source core by setting bit 1 of the Mailbox Send Register. Clearing this bit clears the interrupt to the source core. You can use one write to clear bit 0 and set bit 1 in the Mailbox Send Register, although this is not mandatory. You cannot set bit 1 then clear bit 0 because 11 is an invalid value for the Mailbox Send Register. The Mailbox Send Register can only be written to after the Mailbox Source Register is defined.

Mailbox Data Registers

The Mailbox Data Registers are general-purpose 32-bit registers that contain the message and can only be written to after the Mailbox Source Register is defined. The Mailbox Data Registers are normally written to before sending the message.

Setting mode

The Mailbox Mode Register controls how the acknowledge interrupt is sent back to the source core, and whether the current mailbox is linked to the next mailbox in the IPCM. The Mailbox Mode Register has two bits and you can only write to it after the Mailbox Source Register is defined.

Auto Acknowledge

In Auto Acknowledge mode, an acknowledge interrupt is automatically sent to the source core after the final destination core has cleared its interrupt. Destination cores must clear their interrupts by writing their Channel ID value to the Destination Clear location. This clears their Channel ID from the Mailbox Destination Register. When the Mailbox Destination Register finally reaches zero, indicating that all destination cores have cleared their interrupts, the mailbox automatically detects this, clears bit 0 and sets bit 1 of the Mailbox Send Register. The source core then receives the acknowledge interrupt. The data associated with an Auto Acknowledge is the same as that for the original message. You can use Auto Acknowledge mode for 1-32 destination cores.

Note

You can use Auto Acknowledge when the system contains just two cores, a source core and a destination core.

When Auto Acknowledge mode is disabled, the acknowledge interrupt is optional. The destination core must clear its interrupt by clearing bit 0 of the Mailbox Send Register. Only when the destination core sets bit 1 of the Mailbox Send Register does the source core obtain its acknowledge interrupt, indicating that the destination core has finished with the message. You can only disable Auto Acknowledge mode when there is only one destination core, where there is also a possibility of updating the message for the acknowledge.

Auto Link

Auto Link provides a mechanism to link mailboxes together so that when a message is acknowledged in one mailbox, the next message is sent from the linked mailbox instead of interrupting the source core. When Auto Link is enabled, the destination core clears bit 0 and sets bit 1 of the Mailbox Send Register in the usual way, but the acknowledge interrupt to the source core is masked out and Mailbox Send Register bit 0 is set in the next mailbox, sending that message.

In this mode, a source core can allocate multiple mailboxes to itself, link them together by setting the Auto Link bits and preload messages in all the mailboxes. When the first message is sent, it is not acknowledged until all the messages have been sent. There is no restriction on the destinations of these messages or whether Auto Acknowledge is enabled when Auto Link is used. In the IPCM, Mailbox0 can be linked to Mailbox1, which in turn can be linked to Mailbox2, up to Mailbox31. For example, if you want to link Mailbox0, Mailbox1, and Mailbox2, set the Auto Link bits in Mailbox0 and Mailbox1. Do not set the Auto Link bit in Mailbox2, to enable the acknowledge interrupt to be sent back to the source core.

When Auto Link is disabled, the source core is interrupted if an acknowledge interrupt is sent that has no effect on any other mailbox.

Note

When using Auto Link with Auto Acknowledge, the mailbox automatically sets Mailbox Send Register bit 1 in the first mailbox to send the acknowledge back to the source core but, because Auto Link is also set, the mailbox automatically sets Mailbox Send Register bit 0 in the linked mailbox.

Interrupts and status Registers

When a core receives an IPCM interrupt, it determines which mailbox triggered it by reading the Masked Interrupt Status Register related to that interrupt line. Each Masked Interrupt Status Register contains up to 32 bits, each bit referring to a single mailbox.

If a core is using a mailbox in polled mode, it can use the Raw Interrupt Status Register to indicate which mailbox requires attention.

In Figure 2.4, each mailbox contains up to seven data registers to hold the message. Every mailbox instance with a single IPCM must have the same number of data registers.

Figure 2.4. Mailbox interrupt mapping to IPCM interrupt outputs

Each mailbox can generate up to 32 interrupts, one for each Channel ID. The number of interrupts defines the number of bits in the Mailbox Source Register, Mailbox Destination Register, and Mailbox Mask Register. For example, in Figure 2.4, the IPCM has 32 interrupt outputs. Mailbox0 generates bit 0 of the IPCMMIS0-31 buses, while Mailbox31 generates bit 31 of the IPCMMIS0-31 buses.

Multiple mailboxes are grouped together as shown in Figure 2.4 to form the 32-bit IPCM interrupt bus, IPCMINT[31:0]. All the interrupt bits from each mailbox relating to a single Channel ID are grouped together to form the masked interrupt status buses, IPCMMIS0[31:0] to IPCMMIS31[31:0]. The bits within these buses are then ORed together to form the IPCM interrupt bus, IPCMINT[31:0].

Configuration Status Register

The three configurable parameters for the IPCM are:

  • number of mailboxes, 1-32

  • number of data registers per mailbox, 0-7

  • number of interrupts, 1-32.

The configuration options that you choose define the read-only Configuration Status Register, enabling software to determine the IPCM configuration by reading this register. This enables a generic IPCM software driver to determine how to use each IPCM instance within a system.

To define the IPCM configuration, tie off the MBOXNUM, INTNUM, and DATANUM input pins as follows:

Number of mailboxes

Program the number of active mailboxes by tying off the MBOXNUM input bus (Table 2.2).

Table 2.2. Configuring number of mailboxes

Number of mailboxesMBOXNUM
16'b000001
26'b000010
36'b000011
46'b000100
56'b000101
66'b000110
76'b000111
86'b001000
96'b001001
106'b001010
116'b001011
126'b001100
136'b001101
146'b001110
156'b001111
166'b010000
176'b010001
186'b010010
196'b010011
206'b010100
216'b010101
226'b010110
236'b010111
246'b011000
256'b011001
266'b011010
276'b011011
286'b011100
296'b011101
306'b011110
316'b011111
326'b100000

Note

Any setting of MBOXNUM other than the values shown in Table 2.2 is unsupported.

Number of interrupts

Program the number of active interrupt outputs by tying off the INTNUM input bus (Table 2.3).

Table 2.3. Configuring number of interrupts

Number of mailboxesINTNUM
16'b000001
26'b000010
36'b000011
46'b000100
56'b000101
66'b000110
76'b000111
86'b001000
96'b001001
106'b001010
116'b001011
126'b001100
136'b001101
146'b001110
156'b001111
166'b010000
176'b010001
186'b010010
196'b010011
206'b010100
216'b010101
226'b010110
236'b010111
246'b011000
256'b011001
266'b011010
276'b011011
286'b011100
296'b011101
306'b011110
316'b011111
326'b100000

Note

Any setting of INTNUM other than the values shown in Table 2.3 is unsupported.

Number of data registers in each mailbox

Program the number of active data registers in each mailbox by tying off the DATANUM input bus (Table 2.4).

Table 2.4. Configuring number of data registers

Number of mailboxesDATANUM
03’b000
13'b001
23'b010
33'b011
43'b100
53'b101
63'b110
73'b111

Note

Any setting of DATANUM other than the values shown in Table 2.4 is unsupported.

Usage constraints

There are several valid use models for a mailbox and some constraints under which they can be used. Messages can be sent to:

Multiple cores

If a message is sent to multiple cores, you must use the Auto Acknowledge feature and data must not be modified for the acknowledge. Destination cores must clear their interrupts by writing their Channel ID to the Destination Clear Register.

Single core

If there is only a single destination core, the Auto Acknowledge mode is optional. If you disable the Auto Acknowledge mode, the acknowledge is optional, although an acknowledge normally happens, and the Mailbox Data Register can optionally be updated. When Auto Acknowledge is disabled, the destination core must clear its interrupt by clearing bit 0 of the Mailbox Send Register.

You can only use the Auto Link feature when there is an acknowledge. You can use the Auto Link feature with either:

Auto Acknowledge enabled

The mailbox automatically sets the acknowledge when the final destination core clears its interrupt.

Auto Acknowledge disabled

The destination core must send the acknowledge.

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