3.3.8. Mailbox Mask Status Registers

The read-only IPCMxMSTATUS Registers contain the current status of the Mailbox Mask Registers. Each core is assigned its own bit.

When set, the Mailbox Mask Registers enable the interrupts to each core through bit-wise encoding for each of the Channel IDs. These bits reset to 0, disabling the interrupts.

When cleared, the Mailbox Mask Registers disable the interrupts, enabling the cores to use polling rather than interrupts for messaging.

The Mailbox Mask Registers are all cleared when the Mailbox Source Register is cleared.

Table 3.9 lists the register bit assignments.

Table 3.9. IPCMxMSTATUS Register bit assignments

[31:0]Mask Status

Gives the status of the Mailbox Mask Registers.

For each bit position:

1 = Mailbox interrupt enabled

0 = Mailbox interrupt disabled, polling used instead.

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