2.3.1. Messaging from Core0 to Core1

In this example system, there are two cores and four mailboxes. Core0 is the source core and Core1 is the destination core. Core0 uses Channel ID1 and Core1 uses Channel ID2. Core0 sends a message to Core1 using Mailbox0. This example assumes that the IPCM is not in integration test mode. Mailboxes 1-3 are inactive and Auto Acknowledge and Auto Link are disabled. Figure 2.5 shows the configuration.

Figure 2.5. Configuration, messaging from Core0 to Core1

Figure 2.6 shows the messaging sequence.

Figure 2.6. Messaging from Core0 to Core1

In this example, the following sequence occurs:

  1. Core0 gains control of Mailbox?0 and identifies itself as the source core by setting bit 0 in the IPCM0SOURCE Register.

  2. Core0 enables interrupts to Core?0 and Core1 by setting bits 0 and 1 in the IPCM0MSTATUS Register.

  3. Core0 defines the destination core by setting bit 1 in the IPCM0DSTATUS Register.

  4. Core0 programs the data payload, DA7A0000.

  5. Core0 sets Mailbox Send Register bit 0 to trigger the Mailbox0 interrupt to Core?1.

  6. Core1 reads the IPCMRIS1 Register to determine which mailbox caused the interrupt. In this case, only Mailbox0 is indicated.

  7. Core1 reads the data payload.

  8. Core1 optionally updates the data payload with the Acknowledge data, DA7A1111.

  9. Core1 clears bit 0 and sets bit 1 in the IPCM0SEND Register to clear its interrupt and provide the Manual Acknowledge interrupt back to Core0.

  10. Core0 reads the IPCMRIS0 Register to determine which mailbox caused the interrupt. Again, only Mailbox0 is indicated.

  11. Core0 reads the Acknowledge payload data.

  12. Core0 clears bit 1 in the Mailbox Send Register to clear its interrupt.

  13. Core0 releases ownership of the mailbox by clearing the IPCM0SOURCE Register, which in turn clears the IPCM0DSTATUS, IPCM0MSTATUS, and IPCM0DR0 Registers.


Core?0 can hold on to the mailbox to send another data message by not clearing the IPCM0SOURCE Register at step 13.

Copyright © 2003, 2004. ARM Limited. All rights reserved.ARM DDI 0306B