3.3.4. Mailbox Destination Status Registers

The read-only IPCMxDSTATUS Registers contain the current status of the Mailbox Destination Registers.

When set, the Mailbox Destination Registers determine which cores to send the message to through bit-wise encoding using the Channel ID for each core. For cores that use multiple Channel IDs, only a single Channel ID is used per message.

The Mailbox Destination Registers are cleared in Auto Acknowledge Mode by destination cores to clear the mailbox interrupts to each core. When not in Auto Acknowledge mode, the Mailbox Destination Registers are only cleared by the source core when the mailbox is being reassigned. The Mailbox Destination Registers are cleared automatically by the mailbox regardless of which mode it is in when the Mailbox Source Register is cleared.

Table 3.5 lists the register bit assignments.

Table 3.5. IPCMxDSTATUS Register bit assignments

[31:0]Destination Status

Gives the status of the Mailbox Destination Register.

Defines which interrupt output to assert for the message.

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